Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 44
Datasheet Volume One
Signal Descriptions
3.2 PCI Express* Based Interface Signals
Note: PCI Express* Ports 1and 3 Signals are receive and transmit differential pairs.
Table 3-2. Memory Channel Miscellaneous
Signal Name Description
DDR_RESET_C01_N
DDR_RESET_C23_N
System memory reset: Reset signal from processor to DRAM devices on the
DIMMs. DDR_RESET_C01_N is used for memory channel1 while
DDR_RESET_C23_N is used for memory channels 2 and 3.
DDR_SCL_C01
DDR_SCL_C23
SMBus clock for the dedicated interface to the serial presence detect (SPD) and
thermal sensors (TSoD) on the DIMMs. DDR_SCL_C01 is used for memory
channel1 while DDR_SCL_C23 is used for memory channels 2 and 3.
DDR_SDA_C01
DDR_SDA_C23
SMBus data for the dedicated interface to the serial presence detect (SPD) and
thermal sensors (TSoD) on the DIMMs. DDR_SDA_C01 is used for memory
channel1 while DDR_SDA_C23 is used for memory channels 2 and 3.
DDR01_VREF
DDR23_VREF
Voltage reference for system memory reads. DDR01_VREF is used for memory
channel1 while DDR23_VREF is shared by memory channels 2 and 3.
DDR01_VREFDQ[1]
DDR23_VREFDQ[1:0]
Voltage reference for system memory writes. DDR01_VREFDQ[1] is used for
memory channel1. DDR23_VREFDQ[0] is used for channel 2 and
DDR23_VREFDQ[1] for channel 3. These signal levels are adjusted by MRC to
optimize timing margins.
DDR{01/23}_RCOMP[2:0] System memory impedance compensation. Impedance compensation must be
terminated on the system board using a precision resistor. See the Platform
Design Guide for implementation details.
DRAM_PWR_OK_C01
DRAM_PWR_OK_C23
Power good input signal used to indicate that the VCCD power supply is stable
for memory channel 1 and channels 2 & 3.
Table 3-3. PCI Express* Port 1 Signals
Signal Name Description
PE1A_RX_DN[3:0]
PE1A_RX_DP[3:0]
PCIe Receive Data Input
PE1B_RX_DN[7:4]
PE1B_RX_DP[7:4]
PCIe Receive Data Input
PE1A_TX_DN[3:0]
PE1A_TX_DP[3:0]
PCIe Transmit Data Output
PE1B_TX_DN[7:4]
PE1B_TX_DP[7:4]
PCIe Transmit Data Output
Table 3-4. PCI Express* Port 3 Signals (Sheet 1 of 2)
Signal Name Description
PE3A_RX_DN[3:0]
PE3A_RX_DP[3:0]
PCIe Receive Data Input
PE3B_RX_DN[7:4]
PE3B_RX_DP[7:4]
PCIe Receive Data Input
PE3C_RX_DN[11:8]
PE3C_RX_DP[11:8]
PCIe Receive Data Input
PE3D_RX_DN[15:12]
PE3D_RX_DP[15:12]
PCIe Receive Data Input
PE3A_TX_DN[3:0]
PE3A_TX_DP[3:0]
PCIe Transmit Data Output