Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 43
Datasheet Volume One
Signal Descriptions
3 Signal Descriptions
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category.
3.1 System Memory Interface Signals
Table 3-1. Memory Channel DDR1, DDR2, DDR3
Signal Name Description
DDR{1/2/3}_BA[2:0] Bank Address. Defines the bank which is the destination for the current
Activate, Read, Write, or Precharge command.
DDR{1/2/3}_CAS_N Column Address Strobe.
DDR{1/2/3}_CKE[3:0] Clock Enable.
DDR{1/2/3}_CLK_DN[3:0]
DDR{1/2/3}_CLK_DP[3:0]
Differential clocks to the DIMM. All command and control signals are valid on
the rising edge of clock.
DDR{1/2/3}_CS_N[7:0] Chip Select. Each signal selects one rank as the target of the command and
address.
DDR{1/2/3}_DQ[63:0] Data Bus. DDR3 Data bits.
DDR{1/2/3}_DQS_P[17:0]
DDR{1/2/3}_DQS_N[17:0]
Data strobes. Differential pair, Data/ECC Strobe. Differential strobes latch
data/ECC for each DRAM. Different numbers of strobes are used depending on
whether the connected DRAMs are x4,x8. Driven with edges in center of data,
receive edges are aligned with data edges.
DDR{1/2/3}_ECC[7:0] Check bits. An error correction code is driven along with data on these lines for
DIMMs that support that capability
DDR{1/2/3}_MA[15:0] Memory Address. Selects the Row address for Reads and writes, and the
column address for activates. Also used to set values for DRAM configuration
registers.
DDR{1/2/3}_PAR Odd parity across Address and Command.
DDR{1/2/3}_ODT[3:0] On Die Termination. Enables DRAM on die termination during Data Write or
Data Read transactions.
DDR{1/2/3}_PAR_ERR_N Parity Error detected by Registered DIMM (one for each channel).
DDR{1/2/3}_RAS_N Row Address Strobe.
DDR{1/2/3}_WE_N Write Enable.