Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 4
Datasheet Volume One
2.11.2 I/O Signal Quality Specifications...............................................................38
2.11.3 Intel
®
QuickPath Interconnect Signal Quality Specifications ......................... 38
2.11.4 Input Reference Clock Signal Quality Specifications.....................................38
2.11.5 Overshoot/Undershoot Tolerance..............................................................38
2.11.5.1 Overshoot/Undershoot Magnitude ............................................... 39
2.11.5.2 Overshoot/Undershoot Pulse Duration ......................................... 39
2.11.5.3 Activity Factor..........................................................................39
2.11.5.4 Reading Overshoot/Undershoot Specification Tables ...................... 40
2.11.5.5 Compliance to Overshoot/Undershoot Specifications ......................40
2.12 C-State Power .................................................................................................. 42
3 Signal Descriptions.................................................................................................. 43
3.1 System Memory Interface Signals........................................................................ 43
3.2 PCI Express* Based Interface Signals...................................................................44
3.3 DMI2/PCI Express* Port 0 Signals ....................................................................... 45
3.4 Intel® QuickPath Interconnect Signals ................................................................. 45
3.5 PECI Signal ......................................................................................................46
3.6 System Reference Clock Signals..........................................................................46
3.7 JTAG and TAP Signals ........................................................................................46
3.8 Serial VID Interface (SVID) Signals...................................................................... 46
3.9 Processor Asynchronous Sideband and Miscellaneous Signals .................................. 47
3.10 Processor Power and Ground Supplies..................................................................49
4 Processor Land Listing.............................................................................................51
4.1 Land Listing by Name ........................................................................................ 51
Figures
1-1 Two-Socket Processor Platform ........................................................................... 12
2-1 Input Device Hysteresis .....................................................................................16
2-2 VCCIN Static and Transient Tolerance Loadlines ....................................................29
2-3 VCCIN Overshoot Example Waveform ..................................................................30
2-4 BCLK{0/1} Differential Clock Crosspoint Specification ............................................35
2-5 BCLK{0/1} Differential Clock Measurement Points for Duty Cycle and Period............. 36
2-6 BCLK{0/1} Differential Clock Measurement Points for Edge Rate..............................36
2-7 BCLK{0/1} Differential Clock Measurement Point for Ringback ................................36
2-8 BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point
and Swing........................................................................................................ 37
2-9 BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point .................37
2-10 Maximum Acceptable Overshoot/Undershoot Waveform.......................................... 41
Tables
1-1 Processor Datasheet Volume Structure..................................................................7
1-3 Related Documents and Specifications....................................................................8
1-2 Processor Documents...........................................................................................8
2-1 Power and Ground Lands....................................................................................17
2-2 SVID Address Usage.......................................................................................... 18
2-3 Signal Description Buffer Types...........................................................................19
2-4 Signal Groups................................................................................................... 19
2-5 Signals with On-Die Termination .........................................................................22
2-6 Power-On Configuration Option Lands .................................................................. 22
2-7 Fault Resilient Booting (Output Tri-State) Signals ..................................................23
2-8 Processor Absolute Minimum and Maximum Ratings...............................................25
2-9 Storage Condition Ratings ..................................................................................25
2-10 Voltage Specification..........................................................................................26
2-11 Processor Power Supply Current Specifications......................................................27