Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 37
Datasheet Volume One
Electrical Specifications
2.11 Signal Quality
Data transfer requires the clean reception of data signals and clock signals. Ringing
below receiver thresholds, non-monotonic signal edges, and excessive voltage swings
will adversely affect system timings. Ringback and signal non-monotonicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines.
Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate
oxide integrity, and can cause device failure if absolute voltage limits are exceeded.
Overshoot and undershoot can also cause timing degradation due to the build up of
inter-symbol interference (ISI) effects.
For these reasons, it is crucial that the designer work towards a solution that provides
acceptable signal quality across all systematic variations encountered in volume
manufacturing.
This section documents signal quality metrics used to derive topology and routing
guidelines through simulation. All specifications are specified at the processor die (pad
measurements).
Specifications for signal quality are for measurements at the processor core only and
are only observable through simulation. Therefore, proper simulation is the only way to
verify proper timing and signal quality.
Figure 2-8. BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point
and Swing
Figure 2-9. BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point
V
CROSS MAX
= 550mV
V
CROSS MIN
= 250mV
BCLK_DN
BCLK_DP
V
MIN
= -0.30V
V
MAX
= 1.40V
V
CROSS DELTA
= 140 mV
BCLK_DN
BCLK_DP