Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 35
Datasheet Volume One
Electrical Specifications
2.9.4.2 DMI2/PCI Express* DC Specifications
The processor DC specifications for the DMI2/PCI Express* are available in the PCI
Express Base Specification 2.0 and 1.0. This document will provide only the processor
exceptions to the PCI Express Base Specification 2.0 and 1.0.
2.9.4.3 Intel
®
QuickPath Interconnect DC Specifications
Intel
®
QuickPath Interconnect specifications are defined at the processor lands. Refer
to the Platform Design Guide for specific implementation details. In most cases,
termination resistors are not required as these are integrated into the processor silicon.
The processor DC specifications for the Intel
®
QPI interface are available in the Intel
®
QuickPath Interconnect V1.1 Base Electrical Specification and Validation Methodologies.
This document will provide only the processor exceptions to the Intel
®
QuickPath
Interconnect V1.1 Base Electrical Specification and Validation Methodologies.
2.9.4.4 Reset and Miscellaneous Signal DC Specifications
For a power-on Reset, RESET_N must stay active for at least 3.5 millisecond after V
CCIN
and BCLK{0/1} have reached their proper specifications. RESET_N must not be kept
asserted for more than 100 ms while PWRGOOD is asserted. RESET_N must be held
asserted for at least 3.5 millisecond before it is deasserted again. RESET_N must be
held asserted before PWRGOOD is asserted. This signal does not have on-die
termination and must be terminated on the system board.
2.10 System Reference Clock (BCLK{0/1}) Waveforms
Figure 2-4. BCLK{0/1} Differential Clock Crosspoint Specification
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
200
250
300
350
400
450
500
550
600
650
VHavg (mV)
Crossing Point (mV)
550 mV
250 mV
250 + 0.5 (VHavg - 700)
550 + 0.5 (VHavg - 700)