Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 33
Datasheet Volume One
Electrical Specifications
Note:
1. Measured between V
IL
and V
IH
.
2. Edge rate must be met or the signal must transition monotonically to the asserted state.
Notes:
1. V
CCIO_IN
refers to instantaneous V
CCIO_IN
.
2. Measured at 0.31*V
CCIO_IN
3. Vin between 0V and V
CCIO_IN
4. Refer to the Platform Design Guide for routing design guidelines.
5. These are measured between VIL and VIH.
6. The signal edge rate must be met or the signal must transition monotonically to the asserted state.
V
OL
Output Low Voltage 0.2*V
CCIO_IN
V
R
ON
Buffer On Resistance 4 14 Ω
I
L
Leakage Current 50 200 μA
Output Edge Rate (50 ohm to V
CCIO_IN
, between V
IL
and V
IH
)0.05 0.6 V/ns
Table 2-18. JTAG and TAP Signals DC Specifications
Symbol Parameter Min Max Units Notes
V
IL
Input Low Voltage 0.4*V
CCIO_IN
V
V
IH
Input High Voltage 0.8*V
CCIO_IN
V
V
IL
Input Low Voltage: TCK 0.4*V
CCIO_IN
V
V
IH
Input High Voltage: TCK 0.6*V
CCIO_IN
V
V
OL
Output Low Voltage 0.2*V
CCIO_IN
V
V
Hysteresis
Hysteresis 0.1*V
CCIO_IN
V
R
ON
Buffer On Resistance
BPM_N[7:0], PRDY_N, TDO
414Ω
I
IL
Input Leakage Current 50 200 μA
Input Edge Rate
BPM_N[7:0], EAR_N, PREQ_N, TCK, TDI, TMS, TRST_N
0.05 V/ns 1, 2
Output Edge Rate (50 ohm to V
CCIO_IN
)
BPM_N[7:0], PRDY_N, TDO
0.2 1.5 V/ns 1
Table 2-19. Serial VID Interface (SVID) DC Specifications
Symbol Parameter Min Nom Max Units Notes
V
IL
Input Low Voltage
SVIDDATA, SVIDALERT_N
0.4*V
CCIO_IN
V1
V
IH
Input High Voltage
SVIDDATA, SVIDALERT_N
0.7*V
CCIO_IN
V1
V
OL
Output Low Voltage
SVIDCLK, SVIDDATA
0.2*V
CCIO_IN
V1
V
Hysteresis
Hysteresis 0.05*V
CCIO_IN
V1
R
ON
Buffer On Resistance
SVIDCLK, SVIDDATA
414Ω 2
I
IL
Input Leakage Current 50 200 μA3,4
Input Edge Rate
SVIDALERT_N
0.05 V/ns 5, 6
Output Edge Rate
(50 ohm to V
CCIO_IN
)
0.20 1.5 V/ns 5
Table 2-17. SMBus DC Specifications (Sheet 2 of 2)
Symbol Parameter Min Max Units Notes