Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 32
Datasheet Volume One
Electrical Specifications
Notes:
1. V
CCPECI
supplies the PECI interface. PECI behavior does not affect V
CCPECI
min/max specification
2. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and consequently, be
able to drive its output within safe limits (-0.150 V to 0.275*V
CCPECI
for the low level and 0.725*V
CCPECI
to V
CCPECI
+0.150 V
for the high level).
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional
nodes.
5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum bit
rate at which the interface can operate.
Notes:
1. Specifications apply to all processor frequencies. Parameters are specified at the processor pad.
2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling
edge of BCLK{0/1}_DP.
3. V
Havg
is the statistical average of the VH measured by the oscilloscope.
4. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5. V
Havg
can be measured directly using “Vtop” on Agilent* and “High” on Tektronix oscilloscopes.
6. V
CROSS
is defined as the total variation of all crossing voltages as defined in Note 3.
7. The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP.
8. For Vin between 0 and Vih.
I
SOURCE
High level output source
V
OH
= 0.75 * V
CCPECI
-6.0 mA
I
Leak+
High impedance state leakage to V
CCPECI
(V
leak
=
V
OL
)
50 200 µA 3
R
ON
Buffer On Resistance 20 36 Ω
C
Bus
Bus capacitance per node 10 pF 4,5
V
Noise
Signal noise immunity above 300 MHz 0.100 * V
CCPECI
V
p-p
Output Edge Rate
(50 ohm to V
SS
, between V
IL
and V
IH
)
1.5 4 V/ns
Table 2-16. System Reference Clock (BCLK{0/1}) DC Specifications
Symbol Parameter Min Max
Unit Figure Notes
1
V
BCLK_diff_ih
Input High Voltage
(Differential)
0.150 V 2-7
V
BCLK_diff_il
Input Low Voltage
(Differential)
-0.150 V 2-7
V
cross
(abs) Absolute Crossing Point
(Single Ended)
0.25 0.55 V
2-4
2-8
2, 4, 7
V
cross
(rel) Relative Crossing Point
(Single Ended)
0.25 +0.5*(VH
avg
- 0.7) 0.55 + 0.5*(VH
avg
- 0.7)
V 2-4 3, 4, 5
ΔV
cross
Range of Crossing Points
(Single Ended)
0.140 V 2-9 6
V
TH
Threshold Voltage
(Single Ended)
Vcross - 0.1 Vcross + 0.1
V
I
IL
Input Leakage Current 1.50 μA8
C
pad
Pad Capacitance 1.12 1.70 pF
Table 2-17. SMBus DC Specifications (Sheet 1 of 2)
Symbol Parameter Min Max Units Notes
V
IL
Input Low Voltage 0.3*V
CCIO_IN
V
V
IH
Input High Voltage 0.7*V
CCIO_IN
V
V
Hysteresis
Hysteresis 0.1*V
CCIO_IN
V
Table 2-15. PECI DC Specifications (Sheet 2 of 2)
Symbol Definition and Conditions Min Max Units Figure Notes
1