Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 24
Datasheet Volume One
Electrical Specifications
2.6 Mixing Processors
Intel
®
supports and validates two-processor configurations only in which all processors
operate with the same Intel
®
QuickPath Interconnect frequency, core frequency, power
segment having the same internal cache sizes. Mixing components operating at
different internal clock frequencies is not supported and will not be validated by Intel
®
.
Combining processors from different power segments is also not supported.
Note: Processors within a system must operate at the same frequency per bits [15:8] of the
FLEX_RATIO MSR (Address: 194h); however this does not apply to frequency
transitions initiated due to thermal events, Extended HALT, Enhanced Intel
®
SpeedStep
Technology transitions signal.
Not all operating systems can support dual processors with mixed frequencies. Mixing
processors of different steppings but the same model (as per CPUID instruction) is
supported provided there is no more than one stepping delta between the processors,
for example, S and S+1.
S and S+1 is defined as mixing of two CPU steppings in the same platform where one
CPU is S (stepping) = CPUID.(EAX=01h):EAX[3:0], and the other is S+1 =
CPUID.(EAX=01h):EAX[3:0]+1. The stepping ID is found in EAX[3:0] after executing
the CPUID instruction with Function 01h. Details regarding the CPUID instruction are
provided in Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM)
Volumes 1, 2, and 3.
2.7 Flexible Motherboard Guidelines (FMB)
Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
processor will have over certain time periods. The values are only estimates and actual
specifications for future processors may differ. Processors may or may not have
SMBus DDR_SCL_C01
DDR_SDA_C01
DDR_SCL_C23
DDR_SDA_C23
PE_HP_SCL
PE_HP_SDA
Processor Sideband BPM_N[7:0]
CATERR_N
ERROR_N[2:0]
FIVR_FAULT
MEM_HOT_C01_N
MEM_HOT_C23_N
MSMI_N
PM_FAST_WAKE_N
PROCHOT_N
PECI
PM_FASTWAKE_N
PRDY_N
THERMTRIP_N
SVID SVIDCLK
SVIDDATA
Table 2-7. Fault Resilient Booting (Output Tri-State) Signals (Sheet 2 of 2)
Output Tri-State Signal Groups Signals