Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 23
Datasheet Volume One
Electrical Specifications
3. Signal is sampled at assertion of PWRGOOD .
2.5 Fault Resilient Booting (FRB)
The processor supports both socket and core level Fault Resilient Booting (FRB), which
provides the ability to boot the system as long as there is one processor functional in
the system. One limitation to socket level FRB is that the system cannot boot if the
legacy socket that connects to an active PCH becomes unavailable since this is the path
to the system BIOS. See Table 2-7 for a list of output tri-state FRB signals.
Socket level FRB will tri-state processor outputs via the PROCHOT_N signal. Assertion
of the PROCHOT_N signal through RESET_N de-assertion will tri-state processor
outputs. Note, that individual core disabling is also supported for those cases where
disabling the entire package is not desired.
The processor extends the FRB capability to the core granularity by maintaining a
register in the uncore so that BIOS or another entity can disable one or more specific
processor cores.
Table 2-7. Fault Resilient Booting (Output Tri-State) Signals (Sheet 1 of 2)
Output Tri-State Signal Groups Signals
Intel
®
QPI QPI0_CLKTX_DN[1:0]
QPI0_CLKTX_DP[1:0]
QPI0_DTX_DN[19:0]
QPI0_DTX_DP[19:0]
QPI1_CLKTX_DN[1:0]
QPI1_CLKTX_DP[1:0]
QPI1_DTX_DN[19:0]
QPI1_DTX_DP[19:0]
PCI Express* PE1A_TX_DN[3:0]
PE1A_TX_DP[3:0]
PE1B_TX_DN[7:4]
PE1B_TX_DP[7:4]
PE2A_TX_DN[3:0]
PE2A_TX_DP[3:0]
PE2B_TX_DN[7:4]
PE2B_TX_DP[7:4]
PE2C_TX_DN[11:8]
PE2C_TX_DP[11:8]
PE2D_TX_DN[15:12]
PE2D_TX_DP[15:12]
PE3A_TX_DN[3:0]
PE3A_TX_DP[3:0]
PE3B_TX_DN[7:4]
PE3B_TX_DP[7:4]
PE3C_TX_DN[11:8]
PE3C_TX_DP[11:8]
PE3D_TX_DN[15:12]
PE3D_TX_DP[15:12]
PE_HP_SCL
PE_HP_SDA
DMI2 DMI_TX_DN[3:0], DMI_TX_DP[3:0]