Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 18
Datasheet Volume One
Electrical Specifications
must be taken in the baseboard design to ensure that the voltages provided to the
processor remain within the specifications listed in Table 2-10. Failure to do so can
result in timing violations or reduced operational lifetime of the processor. For
requirements and implementation details, refer to the Platform Design Guide.
2.2.9.3 Voltage Identification (VID)
The target voltage level or the VID setting is transmitted via the SVID bus from the
processor to the voltage regulator controller chip. The VID settings are the nominal
voltages to be delivered to the processor's lands. VID codes will vary as a function of
temperature and current load changes in order to minimize power and maximize
performance of the processor. The processor specifies the VID required from the
voltage regulator to operate at desired frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
processor units with the same core frequency may have different default VID settings.
If the processor socket is empty (SKTOCC_N high), or a “not supported” response is
received from the SVID bus, then the voltage regulation circuit cannot supply the
voltage that is requested, the voltage regulator must disable itself or not power on.
Vout MAX register (30h) is programmed by the processor to set the maximum
supported VID code and if the programmed VID code is higher than the VID supported
by the VR, then VR will respond with a “not supported” acknowledgement.
2.2.9.3.1 SVID Voltage Regulator Addressing
The processor addresses two voltage rail control segments (V
CCIN
and V
CCD
). The SVID
data packet contains a 4-bit address encoding as shown in Table 2-2
Notes:
1. Consult VR vendor for determining the physical address assignment method for their controllers.
2. VR addressing is assigned on a per voltage rail basis.
3. Dual VR controllers have two addresses with the lowest order address, always being the higher phase
count.
4. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not
used.
2.2.10 Reserved or Unused Signals
All Reserved (RSVD) signals must not be connected. Connection of these signals to
V
CCIN
, V
CCD
, V
CCIO_IN,
V
CCPECI
,
V
SS
, or to any other signal (including each other) can result
in component malfunction or incompatibility with future processors.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
SS
). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
Table 2-2. SVID Address Usage
PWM Address (HEX) Processor Supply
00 V
CCIN
01 NA
02 V
CCD
03 N/A