Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 17
Datasheet Volume One
Electrical Specifications
2.2.7 JTAG and Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the JTAG and Test Access
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
2.2.8 Processor Sideband Signals
The processor include asynchronous sideband signals that provide asynchronous input,
output or I/O signals between the processor and the platform or Platform Controller
Hub. Details can be found in Table 2-4 and the platform design guide.
All Processor Asynchronous Sideband input signals are required to be
asserted/deasserted for a defined number of BCLKs in order for the processor to
recognize the proper signal state.
2.2.9 Power, Ground and Sense Signals
Processors also include power and ground inputs and voltage sense points. Details can
be found in Table 2-4 and the Platform Design Guide.
2.2.9.1 Power and Ground Lands
All V
CCIN
,
V
CCD
,
,
V
CCIO_IN
and V
CCPECI
lands must be connected to their respective
processor power planes, while all V
SS
lands must be connected to the system ground
plane. Refer to the platform design guide for decoupling, voltage plane and routing
guidelines for each power supply voltage.
For clean on-chip power distribution, processors include lands for all required voltage
supplies. These are listed in Table 2-1.
2.2.9.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full power states. This may
cause voltages on power planes to sag below their minimum values if bulk decoupling is
not adequate. Large electrolytic bulk capacitors (C
BULK
), help maintain the output
voltage during current transients, for example coming out of an idle condition. Care
Table 2-1. Power and Ground Lands
Power and
Ground
Lands
Number of
Lands
Comments
V
CCIN
107 Each V
CCIN
land must be connected to the voltage supply providing input to the
integrated voltage regulators. The operating voltage is requested via by the SVID
interface.
V
CCD
16 Each V
CCD
land is connected to a switchable supply that provides power to the
processor DDR3 interface. This supply also powers the DDR3 memory subsystem.
V
CCD
is also controlled by the SVID Bus
V
CCIO_IN
1 Connected to Miscellaneous I/O voltage supply.
V
CCPECI
1 Connected to Miscellaneous I/O voltage supply.
V
SS
417 Ground