Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 16
Datasheet Volume One
Electrical Specifications
2.2.5 Platform Environmental Control Interface (PECI)
PECI is an Intel
®
proprietary interface that provides a communication channel between
Intel
®
processors and chipset components to external system management logic and
thermal monitoring devices. The processor integrates a Digital Thermal Sensor (DTS)
that reports a relative die temperature as an offset from Thermal Control Circuit (TCC)
activation temperature. Temperature sensors located throughout the die are
implemented as analog-to-digital converters calibrated at the factory. PECI provides an
interface for external devices to read processor temperature, perform processor
manageability functions, and manage processor interface tuning and diagnostics.
The PECI interface operates at a nominal voltage set by V
CCPECI
. The DC electrical
specifications shown in Table 2-15.
2.2.5.1 Input Device Hysteresis
The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. Refer to Figure 2-1 and Table 2-15.
2.2.6 System Reference Clocks (BCLK{0/1}_DP,
BCLK{0/1}_DN)
The processor core, processor uncore, Intel
®
QuickPath Interconnect link, PCI Express*
and DDR3 memory interface frequencies are generated from BCLK{0/1}_DP and
BCLK{0/1}_DN signals. There is no relationship between core frequency and Intel
®
QuickPath Interconnect link frequency. The processor maximum core frequency, Intel
®
QuickPath Interconnect link frequency and DDR memory frequency are set during
manufacturing. It is possible to override the processor core frequency setting using
BIOS configuration software. This permits operation at frequencies lower than the
factory set maximum frequencies.
The processor core frequency is configured during reset by using values stored within
the device during manufacturing.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,
BCLK{0/1}_DN inputs are provided in Table 2-16.
Figure 2-1. Input Device Hysteresis