Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 15
Datasheet Volume One
Electrical Specifications
2 Electrical Specifications
2.1 Integrated Voltage Regulators
The Intel® Xeon® Processor E5-2400 v3 Product Family introduces platform innovation
by integrating several voltage regulators into the processor. Integrating these voltage
regulators reduces cost and simplifies system design by reducing the number of
external regulators on the system board.
The V
CCIN
voltage rail supplies the input source to the integrated voltage regulators
powering cores, cache and system agents. This integration improves regulation of on-
die voltages optimizing performance and power savings. The V
CCIN
rail is supplied by an
external voltage regulator.
2.2 Processor Signaling
The processor includes 1356 lands, which utilize various signaling technologies. Signals
are grouped by electrical characteristics and buffer type into various signal groups.
These include DDR3 (Reference Clock, Command, Control, and Data), PCI Express*,
DMI2, Intel
®
QuickPath Interconnect, Platform Environmental Control Interface (PECI),
System Reference Clock, SMBus, JTAG and Test Access Port (TAP), SVID Interface,
Processor Asynchronous Sideband, Miscellaneous, and Power/Other signals. Refer to
Table 2-4 for details.
Intel strongly recommends performing analog simulations of all interfaces. Refer to
Section 1.2, “Related Documents” for signal integrity model availability.
2.2.1 System Memory Interface Signals
The system memory interface utilizes DDR3 technology, consisting of numerous signal
groups. These include: Reference Clocks, Command Signals, Control Signals, and Data
Signals. Each group consists of numerous signals, which may utilize various signaling
technologies. Refer to Table 2-4 for further details. Throughout this chapter the system
memory interface maybe referred to as DDR3.
2.2.2 PCI Express* Signals
The PCI Express Signal Group consists of PCI Express* ports 1, 2, and 3, and PCI
Express* miscellaneous signals. Refer to Table 2-4 for further details.
2.2.3 DMI2/PCI Express* Signals
The Direct Media Interface Gen 2 (DMI2) sends and receives packets and/or commands
to the PCH. DMI2 is an extension of the standard PCI Express Specification. The
DMI2/PCI Express interface consist of DMI2 receive and transmit input/output signals.
Refer to Table 2-4 for further details.
2.2.4 Intel
®
QuickPath Interconnect (Intel
®
QPI)
The processor provides one Intel
®
QPI port for high speed serial transfer between
processors. The port consists of two uni-directional links (for transmit and receive). A
high-speed differential signaling scheme is utilized.