Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 13
Datasheet Volume One
Overview
— Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM
• Memory thermal monitoring support for DIMM temperature via two memory
signals, MEM_HOT_C{01/23}_N
1.5.2 PCI Express*
• Up to 24 lanes of PCI Express*
• Compliant to the PCI Express* Base Specification, Revision 3.0 (PCIe* 3.0)
• Configurable for up to six independent ports
• 4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0),
also can be downgraded to x2 or x1
• Reduced link width negotiation supported:
— x16 port (Port 3) may negotiate down to x8, x4, x2, or x1
— x8 port (Port 1) may negotiate down to x4, x2, or x1
— x4 port (Port 0) may negotiate down to x2, or x1
— Lane reversal supported with limitations on reduced widths
• Non-Transparent Bridge (NTB) is supported by PCIe Port3a/IOU1. For more details
on NTB mode operation refer to PCI Express Base Specification - Revision 3.0.
1.5.3 Direct Media Interface Gen 2 (DMI2)
• Primary processor interface to the platform controller hub (PCH)
• Link width is exclusively x4 in DMI2 mode
• Operation at PCI Express* 1.0 or 2.0 speeds
1.5.4 Intel
®
QuickPath Interconnect (Intel
®
QPI)
•One Intel
®
QuickPath Interconnect port
• Full width port with 20 data lanes and 1 clock lane
• No bifurcation support
• Differential signaling
• Forwarded clocking with common input reference clock
• Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth)
1.5.5 Platform Environment Control Interface (PECI)
PECI is a single-wire multi-drop interface providing a comm
• Supports operation at up to 2 Mbps data transfers
1.6 Package Summary
The Processor socket type is noted as Socket B3. It is a 45 mm x 42.5 mm FCLGA12
package (LGA1356-3).