Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 12
Datasheet Volume One
Overview
1.4 Processor Feature Overview
1.4.1 Core Feature Overview
• Up to 10 physical cores
• Each core supports two threads (Intel
®
Hyper-Threading Technology), up to 20
threads per socket
• 32-KB instruction and 32-KB data first-level cache (L1) for each core
• 256-KB shared instruction/data mid-level (L2) cache for each core
• Up to 25 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level
cache (LLC), shared among all cores
A rudimentary block diagram is illustrated in Figure with two processors
interconnected to a Platform Controller Hub (PCH).
1.5 Interface Feature Overview
This section presents a limited high-level overview of the physical interfaces of the
Intel® Xeon® Processor E5-2400 v3 Product Family.
1.5.1 System Memory
• Three DDR3 channels
• DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V
• 64-bit wide data plus 8-bits of ECC support for each channel
• Data transfer rates of 800, 1066, 1333, and 1600 MT/s
• Unbuffered DDR3 and registered DDR3 DIMMs
• 1Gb, 2Gb and 4Gb DDR3 DRAM technologies are supported for these devices:
— UDIMMs x8, x16
— RDIMMs x4, x8
Figure 1-1. Two-Socket Processor Platform