Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 10
Datasheet Volume One
Overview
NEBS Network Equipment Building System. NEBS is the most common set of
environmental design guidelines applied to telecommunications equipment in the
United States.
PCH Platform Controller Hub. The next generation chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCU Power Control Unit
PCI Express* 3.0 PCI Express* Generation 3.0
The third generation PCI Express* specification that operates at twice the speed
of PCI Express* 2.0 (8 Gb/s). PCI Express* 3.0 is backward compatible with PCI
Express* 1.0 and 2.0.
PCI Express* 2.0 PCI Express* Generation 2.0
PCI Express* PCI Express* Generation 2.0/3.0
PECI Platform Environment Control Interface
Phit
Physical Unit. Intel
®
QPI terminology defining units of transfer at the physical
layer. 1 Phit is equal to 20 bits in ‘full width mode’ and 10 bits in ‘half width
mode’
Processor The 64-bit, single-core or multi-core component (package)
Core A functional element of the processor capable of executing instructions. Each
core has an instruction cache, data cache, and 256-KB L2 cache. All execution
cores share the L3 cache.
RDIMM Registered Dual In-line Module
Rank A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a DDR3
DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
SSE Intel
®
Streaming SIMD Extensions (Intel
®
SSE)
SKU Stock Keeping Unit (SKU) identifying a particular model having unique attributes.
Electrical, power and thermal specifications for these SKU’s are based on specific
use condition assumptions.
SMBus System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the
system. It is based on the principals of the operation of the I2C* two-wire serial
bus from Philips Semiconductor.
Storage Conditions A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to open air. Under
these conditions, processor land contacts s should not be connected to any
supply voltages, have any I/O buffers biased or receive any clocks. Upon
exposure to “free air” (i.e., unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
TAC Thermal Averaging Constant
TDP Thermal Design Power
TSOD Thermal Sensor on DIMM
UDIMM Unbuffered Dual In-line Module
Uncore The portion of the processor comprised of the shared cache, IMC, HA, PCU,
UBox, and Intel
®
QPI link interface.
Unit Interval Signaling convention that is binary and unidirectional. In this binary signaling,
one bit is sent for every edge of the forwarded clock, whether it be a rising edge
or a falling edge. If a number of edges are collected at instances t
1
, t
2
, t
n
,...., t
k
then the UI at instance “n” is defined as:
UI
n
= t
n
- t
n
- 1
V
CCIN
Voltage rail supplies the input source to the integrated voltage regulators.
V
SS
Processor ground
Term Description