Intel® Xeon® Processor E5-2400 v3 Product Family Datasheet, Volume One: Electrical Volume 1 of 2 January 2015 Reference Number:331592-001
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Table of Contents 1 Overview ................................................................................................................... 7 1.1 Introduction ....................................................................................................... 7 1.3 Terminology ....................................................................................................... 8 1.2 Related Documents .............................................................................................
2.11.2 2.11.3 2.11.4 2.11.5 2.12 I/O Signal Quality Specifications............................................................... 38 Intel® QuickPath Interconnect Signal Quality Specifications ......................... 38 Input Reference Clock Signal Quality Specifications..................................... 38 Overshoot/Undershoot Tolerance.............................................................. 38 2.11.5.1 Overshoot/Undershoot Magnitude ............................................... 39 2.11.5.
2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 4-1 Processor VCCIN Static and Transient Tolerance .................................................... 28 VCCIN Overshoot Specifications .......................................................................... 29 DDR3 and DDR3L Signal DC Specifications............................................................ 30 PECI DC Specifications ...........................................
Revision History Revision Number 001 Description Initial Release Intel® Xeon® Processor E5-2400 v3 Product Family Datasheet Volume One Revision Date January 2015 6
Overview 1 Overview 1.1 Introduction Intel® Xeon® Processor E5-2400 v3 Product Family Datasheet - Volume One provides DC electrical specifications, signal definitions and an overview of processor interfaces. This document is intended to be distributed as a part of a two volume set. The structure and scope of the volumes is provided in Table 1-1.
Overview 1.2 Related Documents The following documents provide additional information related to system design with the Intel® Xeon® Processor E5-2400 v3 Product Family. Table 1-2. Processor Documents Document Number/ Location1 Document Table 1-3. Intel® Xeon® Processor E5 v3 Product Families Datasheet Volume 2; Registers intel.com Intel® Xeon® Processor E5-2400 v3 Product Families Thermal/Mechanical Specification and Design Guide (TMSDG) intel.
Overview Term DTS Description Digital Thermal Sensor ECC Error Correction Code Intel® ® Enhanced SpeedStep Technology Allows the operating system to reduce power consumption when performance is not needed. Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system.
Overview Term Description NEBS Network Equipment Building System. NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States. PCH Platform Controller Hub. The next generation chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. PCU Power Control Unit PCI Express* 3.0 PCI Express* Generation 3.
Overview Term Description VCCD DDR3 power supply for the processor system memory interface.
Overview 1.4 Processor Feature Overview 1.4.1 Core Feature Overview • Up to 10 physical cores • Each core supports two threads (Intel® Hyper-Threading Technology), up to 20 threads per socket • 32-KB instruction and 32-KB data first-level cache (L1) for each core • 256-KB shared instruction/data mid-level (L2) cache for each core • Up to 25 MB last level cache (LLC): up to 2.
Overview — Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM • Memory thermal monitoring support for DIMM temperature via two memory signals, MEM_HOT_C{01/23}_N 1.5.2 PCI Express* • Up to 24 lanes of PCI Express* • Compliant to the PCI Express* Base Specification, Revision 3.0 (PCIe* 3.0) • Configurable for up to six independent ports • 4 lanes of PCI Express* at PCIe* 2.
Overview 1.7 Statement of Volatility (SOV) The Intel® Xeon® Processor E5-2400 v3 Product Family does not retain any end-user data when powered down and/or the processor is physically removed from the socket. 1.8 State of Data The data contained within this document is the most accurate information available by the publication date of this document. Electrical DC specifications are based on estimated I/O buffer behavior.
Electrical Specifications 2 Electrical Specifications 2.1 Integrated Voltage Regulators The Intel® Xeon® Processor E5-2400 v3 Product Family introduces platform innovation by integrating several voltage regulators into the processor. Integrating these voltage regulators reduces cost and simplifies system design by reducing the number of external regulators on the system board. The VCCIN voltage rail supplies the input source to the integrated voltage regulators powering cores, cache and system agents.
Electrical Specifications 2.2.5 Platform Environmental Control Interface (PECI) PECI is an Intel® proprietary interface that provides a communication channel between Intel® processors and chipset components to external system management logic and thermal monitoring devices. The processor integrates a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications 2.2.7 JTAG and Test Access Port (TAP) Signals Due to the voltage levels supported by other components in the JTAG and Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.
Electrical Specifications must be taken in the baseboard design to ensure that the voltages provided to the processor remain within the specifications listed in Table 2-10. Failure to do so can result in timing violations or reduced operational lifetime of the processor. For requirements and implementation details, refer to the Platform Design Guide. 2.2.9.
Electrical Specifications also allow for system testability. Resistor values should be within ± 20% of the impedance of the baseboard trace, unless otherwise noted in the appropriate platform design guidelines. 2.3 Signal Group Summary Signals are grouped by buffer type and similar characteristics as listed in Table 2-3. The buffer type indicates which signaling technology and specifications apply to the signals. Table 2-3.
Electrical Specifications Table 2-4. Signal Groups (Sheet 2 of 3) Differential/Single Ended Signals1 Buffer Type Differential SSTL Input/Output DDR{1/2/3}_DQS_[N/P][17:0] Single ended SSTL Input/Output DDR{1/2/3}_DQ[63:0] DDR{1/2/3}_ECC[7:0] SSTL Input DDR{1/2/3}_PAR_ERR_N DDR3 Miscellaneous Signals2 Single ended CMOS Input Note: Input voltage from cannot exceed 1.08V max. DRAM_PWR_OK_C{01/23} CMOS1.
Electrical Specifications Table 2-4. Signal Groups (Sheet 3 of 3) Differential/Single Ended Signals1 Buffer Type JTAG & TAP Signals Single ended CMOS1.05v Input TCK, TDI, TMS, TRST_N, EAR_N CMOS1.05v Input/Output PREQ_N CMOS1.05v Output PRDY_N Open Drain CMOS Input/Output BPM_N[7:0] Open Drain CMOS Output TDO Serial VID Interface (SVID) Signals Single ended CMOS1.
Electrical Specifications Table 2-5.
Electrical Specifications 3. 2.5 Signal is sampled at assertion of PWRGOOD . Fault Resilient Booting (FRB) The processor supports both socket and core level Fault Resilient Booting (FRB), which provides the ability to boot the system as long as there is one processor functional in the system. One limitation to socket level FRB is that the system cannot boot if the legacy socket that connects to an active PCH becomes unavailable since this is the path to the system BIOS.
Electrical Specifications Table 2-7. 2.
Electrical Specifications specifications equal to the FMB value in the foreseeable future. System designers should meet the FMB values to ensure their systems will be compatible with future processors. 2.8 Absolute Maximum and Minimum Ratings Table 2-8 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications Table 2-9. Storage Condition Ratings (Sheet 2 of 2) Symbol Parameter Min Max Unit Tsustained storage The minimum/maximum device storage temperature for a sustained period of time. -5 40 °C Tshort term storage The ambient storage temperature (in shipping media) for a short period of time. -20 85 °C RHsustained storage The maximum device storage relative humidity for a sustained period of time.
Electrical Specifications 2. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different settings. 3. Voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. A future processor may be developed requiring a nominal voltage 0.95V. 4.
Electrical Specifications Table 2-12. Processor VCCIN Static and Transient Tolerance ICCIN [A] VCCIN_Max [V] VCCIN_Nominal [V] VCCIN_Min [V] Notes 0 VID + 0.025 VID - 0.000 VID - 0.025 1,2,3,4 5 VID + 0.018 VID - 0.007 VID - 0.032 1,2,3,4 10 VID + 0.011 VID - 0.014 VID - 0.039 1,2,3,4 15 VID +0.004 VID - 0.021 VID - 0.046 1,2,3,4 20 VID - 0.003 VID - 0.028 VID - 0.053 1,2,3,4 25 VID - 0.010 VID - 0.035 VID - 0.060 1,2,3,4 30 VID - 0.017 VID - 0.042 VID - 0.
Electrical Specifications Figure 2-2. VCCIN Static and Transient Tolerance Loadlines 2.9.3 Die Voltage Validation VCCIN overshoot events at the processor must meet the specifications in Table 2-13 when measured across the VCCIN_SENSE and VSS_VCCIN_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. 2.9.3.
Electrical Specifications Figure 2-3. VCCIN Overshoot Example Waveform Notes: 1. VOS_MAX is the measured overshoot voltage. 2. TOS_MAX is the measured time duration above VCCIN_MAX(I1). 3. Istep: Load Release Current Step, for example, I2 to I1, where I2 > I1. 4. VCCIN_MAX(I1) = VID + TOB 2.9.4 Signal DC Specifications DC specifications are defined at the processor pads, unless otherwise noted.
Electrical Specifications Table 2-14. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2) Symbol Parameter Min DDR3 Clock Buffer On Resistance RON Nom Max Units Notes1 31 Ω 6 21 Command Signals RON DDR3 Command Buffer On Resistance 16 24 Ω 6 RON DDR3 Reset Buffer On Resistance 25 75 Ω 6 VOL_CMOS1.5v Output Low Voltage DDR_RESET_ C{01/23}_N 0.2*VCCD V 1,2 VOH_CMOS1.5v Output High Voltage DDR_RESET_ C{01/23}_N V 1,2 IIL_CMOS1.5v Input Leakage Current μA 1,2 0.
Electrical Specifications Table 2-15. PECI DC Specifications (Sheet 2 of 2) Symbol Definition and Conditions Min Max Units ISOURCE High level output source VOH = 0.75 * VCCPECI -6.0 ILeak+ High impedance state leakage to VCCPECI (Vleak = VOL) 50 200 µA RON Buffer On Resistance 20 36 Ω CBus Bus capacitance per node VNoise Signal noise immunity above 300 MHz 0.100 * VCCPECI Output Edge Rate (50 ohm to VSS, between VIL and VIH) 1.
Electrical Specifications Table 2-17. SMBus DC Specifications (Sheet 2 of 2) Symbol Parameter VOL Output Low Voltage RON Buffer On Resistance IL Min Units 0.2*VCCIO_IN V 4 14 Ω 50 200 μA 0.05 0.6 V/ns Leakage Current Output Edge Rate (50 ohm to VCCIO_IN, between VIL and VIH) Max Notes Table 2-18.
Electrical Specifications Table 2-20. Processor Asynchronous Sideband DC Specifications Symbol Parameter Min Max Units Notes 0.4*VCCIO_IN V 1,2 V 1,2 200 μA 1,2 CMOS1.05v Signals VIL_CMOS1.05v Input Low Voltage VIH_CMOS1.05v Input High Voltage IIL_CMOS1.05v Input Leakage Current 0.6*VCCIO_IN 50 Open Drain CMOS (ODCMOS) Signals VIL_ODCMOS Input Low Voltage MEM_HOT_C{01/23}_N, PROCHOT_N 0.3*VCCIO_IN V 1,2 VIL_ODCMOS Input Low Voltage CATERR_N, MSMI_N, PM_FAST_WAKE_N 0.
Electrical Specifications 2.9.4.2 DMI2/PCI Express* DC Specifications The processor DC specifications for the DMI2/PCI Express* are available in the PCI Express Base Specification 2.0 and 1.0. This document will provide only the processor exceptions to the PCI Express Base Specification 2.0 and 1.0. 2.9.4.3 Intel® QuickPath Interconnect DC Specifications Intel® QuickPath Interconnect specifications are defined at the processor lands.
Electrical Specifications Figure 2-5. BCLK{0/1} Differential Clock Measurement Points for Duty Cycle and Period Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) 0.0V BCLK Figure 2-6. BCLK{0/1} Differential Clock Measurement Points for Edge Rate Rise Edge Rate Fall Edge Rate VIH = +150 mV 0.0V VIL = -150 mV BCLK Figure 2-7. BCLK{0/1} Differential Clock Measurement Point for Ringback T STABLE VRB-Differential VIH = +150 mV VRB = +100 mV 0.
Electrical Specifications Figure 2-8. BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point and Swing VMAX = 1.40V BCLK_DN VCROSS MAX = 550mV VCROSS MIN = 250mV BCLK_DP VMIN = -0.30V Figure 2-9. BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point BCLK_DN VCROSS DELTA = 140 mV BCLK_DP 2.11 Signal Quality Data transfer requires the clean reception of data signals and clock signals.
Electrical Specifications 2.11.1 DDR3 Signal Quality Specifications Various scenarios for the DDR3 Signals have been simulated to generate a set of layout guidelines which are available in the Platform Design Guide. Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The overshoot/undershoot specifications limit transitions beyond specified maximum voltages or VSS due to the fast signal edge rates.
Electrical Specifications Table 2-22. Processor I/O Overshoot/Undershoot Specifications (Sheet 2 of 2) Signal Group DDR3 Minimum Undershoot Maximum Overshoot Overshoot Duration Undershoot Duration Notes -0.2 * VCCD 1.2 * VCCD 0.25*TCH 0.1*TCH 1,2,3 -0.3V 1.15V N/A N/A 1,2 -0.42V VCCIO_IN + 0.28 1.25 ns 0.5 ns 4 System Reference Clock (BCLK{0/1}) PWRGOOD Signal Notes: 1. These specifications are measured at the processor pad. 2.
Electrical Specifications 2.11.5.4 Reading Overshoot/Undershoot Specification Tables The overshoot/undershoot specification for the processor is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1.
Electrical Specifications Figure 2-10.
Electrical Specifications 2.12 C-State Power Table 2-24 lists the package level C-State power specifications for each processor SKUs. This represents the total power dissipated by the processor component in each C-State. Table 2-24. Processor Package C-State Power Specifications Processor TDP / Core count 1 C1E (W) 3 C3 (W) 3 C6 (W) 2 35 28 13 LV70W-10C LV65W-8C 1S 30 24 13 LV55W-8C 30 24 12 LV50W-6C 27 23 12 LV45W-4C 27 23 12 Notes: 1. SKUs are subject to change.
Signal Descriptions 3 Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. 3.1 System Memory Interface Signals Table 3-1. Memory Channel DDR1, DDR2, DDR3 Signal Name DDR{1/2/3}_BA[2:0] Description Bank Address. Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. DDR{1/2/3}_CAS_N Column Address Strobe. DDR{1/2/3}_CKE[3:0] Clock Enable.
Signal Descriptions Table 3-2. Memory Channel Miscellaneous Signal Name Description DDR_RESET_C01_N DDR_RESET_C23_N System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C01_N is used for memory channel1 while DDR_RESET_C23_N is used for memory channels 2 and 3. DDR_SCL_C01 DDR_SCL_C23 SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs.
Signal Descriptions Table 3-4. PCI Express* Port 3 Signals (Sheet 2 of 2) Signal Name Table 3-5. Description PE3B_TX_DN[7:4] PE3B_TX_DP[7:4] PCIe Transmit Data Output PE3C_TX_DN[11:8] PE3C_TX_DP[11:8] PCIe Transmit Data Output PE3D_TX_DN[15:12] PE3D_TX_DP[15:12] PCIe Transmit Data Output PCI Express* Miscellaneous Signals Signal Name Description PE_HP_SCL PCI Express* Hot-Plug SMBus Clock: Provides PCI Express* hot-plug support via a dedicated SMBus interface.
Signal Descriptions 3.5 PECI Signal Table 3-8. PECI Signal Signal Name PECI Description PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power and error management. Details regarding the PECI electrical specifications, protocols and functions can be found in the Platform Environment Control Interface Specification. 3.6 System Reference Clock Signals Table 3-9. System Reference Clock (BCLK) Signals 3.
Signal Descriptions Table 3-11. SVID Signals (Sheet 2 of 2) Signal Name 3.9 Description SVIDCLK Serial VID clock. SVIDDATA Serial VID data out. Processor Asynchronous Sideband and Miscellaneous Signals Table 3-12. Processor Asynchronous Sideband Signals (Sheet 1 of 3) Signal Name Description BIST_ENABLE BIST Enable Strap. Input which allows the platform to enable or disable built-in self test (BIST) on the processor. This signal is pulled up on the die, refer to Table 2-5 for details.
Signal Descriptions Table 3-12. Processor Asynchronous Sideband Signals (Sheet 2 of 3) Signal Name MEM_HOT_C01_N MEM_HOT_C23_N Description Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two modes of operation – input and output mode. Input mode is externally asserted and is used to detect external events such as VR_HOT# from the memory voltage regulator and causes the processor to throttle the appropriate memory channels. Output mode is asserted by the processor known as level mode.
Signal Descriptions Table 3-12. Processor Asynchronous Sideband Signals (Sheet 3 of 3) Signal Name Description THERMTRIP_N Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical overtemperature conditions: One, the processor junction temperature has reached a level beyond which permanent silicon damage may occur and Two, the system memory interface has exceeded a critical temperature limit set by BIOS.
Signal Descriptions Table 3-14. Power and Ground Signals (Sheet 2 of 2) Signal Name Description VCCIN_SENSE VSS_VCCIN_SENSE Isolated, low impedance connection to the processor power and ground. These signals must be connected to the voltage regulator feedback circuit, which ensures processor voltage remains within specification. VCCIO_IN Power supply for miscellaneous I/O interfaces of the processor. VCCPECI Power supply for PECI interface of the processor.
Processor Land Listing 4 Processor Land Listing 4.1 Land Listing by Name Note: Table 4-1. This land listing is provided in this document for convenience. Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 3 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 5 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 7 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 9 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 11 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 13 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 15 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 17 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 19 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Name Land Listing (Sheet 21 of 37) Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Listing (Sheet 23 of 37) Land Name Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Name Land Listing (Sheet 25 of 37) Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Name Land Listing (Sheet 27 of 37) Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Name Land Listing (Sheet 29 of 37) Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Name Land Listing (Sheet 31 of 37) Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Name Land Listing (Sheet 33 of 37) Land Number Table 4-1.
Processor Land Listing Table 4-1. Land Name Land Listing (Sheet 35 of 37) Land Number Table 4-1.
Processor Land Listing Table 4-1.
Processor Land Listing Intel® Xeon® Processor E5-2400 v3 Product Family Datasheet Volume One 70
