Datasheet

Interfaces
50 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 v2 Product Families
Datasheet Volume One of Two
• PCU Device ID: This information can be used to uniquely identify the processor
power control unit (PCU) device when combined with the Vendor Identification
register content and remains constant across all SKUs. Refer to the appropriate
register description for the exact processor PCU Device ID value.
• Max Thread ID: The maximum Thread ID data provides the number of supported
processor threads. This value is dependent on the number of cores within the
processor as determined by the processor SKU and is independent of whether
certain cores or corresponding threads are enabled or disabled.
• CPU Microcode Update Revision: Reflects the revision number for the microcode
update and power control unit firmware updates on the processor sample. The
revision data is a unique 32-bit identifier that reflects a combination of specific
versions of the processor microcode and PCU control firmware.
• Machine Check Status: Returns error information as logged by the MCA Error
Source Log register. See Figure 2-26 for details. The power control unit will assert
the relevant bit when the error condition represented by the bit occurs. For
example, bit 29 will be set if the package asserted MCERR, bit 30 is set if the
package asserted IERR and bit 31 is set if the package asserted CAT_ERR_N. The
CAT_ERR_N may be used to signal the occurrence of a MCERR or IERR.
Figure 2-22. Platform ID Data
Platform ID Data
Processor
Flag
Reserved
2
31
0
3
Figure 2-23. PCU Device ID
PCU Device ID Data
RESERVED
031
PCU Device ID
1516
Figure 2-24. Maximum Thread ID
Maximum Thread ID Data
Max Thread
ID
Reserved
3
31
0
4
Figure 2-25. Processor Microcode Revision
CPU microcode and PCU firmware revision
31
0
CPU code patch revision