Datasheet

Overview
Intel
®
Xeon
®
Processor E5-1600/E5-2600/E5-4600 v2 Product Families 19
Datasheet Volume One of Two
1.2.3 Direct Media Interface Gen 2 (DMI2)
• Serves as the chip-to-chip interface to the Intel® C600 Chipset
• The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2
• Operates at PCI Express* 1.0 or 2.0 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of
Interrupt” broadcast message when initiated by the processor.
• Downstream System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
1.2.4 Intel
®
QuickPath Interconnect (Intel
®
QPI)
• Compliant with Intel QuickPath Interconnect (Intel
®
QPI) v1.1 standard
packet formats
• Implements two full width Intel QPI ports
• Full width port includes 20 data lanes and 1 clock lane
• 64 byte cache-lines
• Isochronous access support is not available on any CPU model containing two
home agents.
Note: RAS support depends on processor SKU. For example, Workstation SKUs do
not support sparing or tagging, lockstep mode, mirroring mode, channel
mirroring mode within a socket, error containment.
• Home snoop based coherency
•4-bit Node ID
• 46-bit physical addressing support
• No Intel QuickPath Interconnect bifurcation support
• Differential signaling
• Forwarded clocking
• Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth per port)
— All ports run at same operational frequency
— Reference Clock is 100 MHz
— Slow boot speed initialization at 50 MT/s
• Common reference clocking (same clock generator for both sender and receiver)
•Intel
®
Interconnect Built-In-Self-Test (Intel
®
IBIST) for high-speed testability
• Polarity Inversion and Lane reversal (Rx side only)
1.2.5 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH).