Datasheet

Overview
Intel
®
Xeon
®
Processor E5-1600/E5-2600/E5-4600 v2 Product Families 17
Datasheet Volume One of Two
— Data scrambling with address to ease detection of write errors to an
incorrect address.
— Error reporting via Machine Check Architecture
— Read Retry during CRC error handling checks by iMC
— Channel mirroring within a socket
— Channel Mirroring mode is supported on memory channels 0 & 1 and
channels 2 & 3
— Error Containment Recovery
• Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
• Memory thermal monitoring support for DIMM temperature via two memory
signals, MEM_HOT_C{01/23}_N
1.2.2 PCI Express*
• The PCI Express* port(s) are fully-compliant to the PCI Express* Base
Specification, Revision 3.0 (PCIe 3.0)
• Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s)
• Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express*
devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports
• 4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0),
also can be downgraded to x2 or x1
• Negotiating down to narrower widths is supported, see Figure 1-4:
— x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1.
— x8 port (Port 1) may negotiate down to x4, x2, or x1.
— x4 port (Port 0) may negotiate down to x2, or x1.
— When negotiating down to narrower widths, there are caveats as to how lane
reversal is supported.
• Non-Transparent Bridge (NTB) is supported by PCIe Port3a/IOU1. For more details
on NTB mode operation refer to PCI Express Base Specification - Revision 3.0:
— x4, x8 or x16 widths and at PCIe* 1.0, 2.0, 3.0 speeds
— Two usage models; NTB attached to a Root Port or NTB attached to
another NTB
— Supports three 64-bit BARs
— Supports posted writes and non-posted memory read transactions across
the NTB
— Supports INTx, MSI and MSI-X mechanisms for interrupts on both side of NTB
in upstream direction only
• Address Translation Services (ATS) 1.0 support
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.