Datasheet

Datasheet 65
Electrical Specifications
5. The V
TTA,
and V
TTD
voltage specification requirements are measured across the remote sense pin pairs (VTTD_SENSE and
VSS_VTTD_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 MΩ
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external
noise from the system is not coupled in the scope probe.
6. The V
SA
voltage specification requirements are measured across the remote sense pin pairs (VSA_SENSE and
VSS_VSA_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 MΩ
minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external
noise from the system is not coupled in the scope probe.
7. The processor should not be subjected to any static V
CC
level that exceeds the V
CC_MAX
associated with any particular current.
Failure to adhere to this specification can shorten processor lifetime.
8. Minimum V
CC
and maximum I
CC
are specified at the maximum processor case temperature (T
CASE
). I
CC_MAX
is specified at the
relative V
CC_MAX
point on the V
CC
load line. The processor is capable of drawing I
CC_MAX
for up to 5 seconds.
9. The processor should not be subjected to any static V
TTA,
V
TTD
level that exceeds the V
TT_MAX
associated with any particular
current. Failure to adhere to this specification can shorten processor lifetime.
10. This specification represents the V
CC
reduction or V
CC
increase due to each VID transition, see Section 7.1.8.3.
11. Baseboard bandwidth is limited to 20 MHz.
12. N/A
13. DC + AC + Ripple = Total Tolerance
14. For Power State Functions see Section 7.1.8.3.5.
15. V
SA_VID
does not have a loadline, the output voltage is expected to be the VID value.
16. V
CCD
tolerance at processor pins. Tolerance for VR at remote sense is ±3.3%*V
CCD
.
17. The V
CCPLL
, V
CCD01
, V
CCD23
voltage specification requirements are measured across vias on the platform. Choose V
CCPLL
,
V
CCD01
, or V
CCD23
vias close to the socket and measure with a DC to 100MHz bandwidth oscilloscope limit (or DC to 20 MHz
for older model oscilloscopes), using 1.5 pF maximum probe capacitance, and 1M Ω minimum impedance. The maximum
length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in
the scope probe.
18. V
CC
has a Vboot setting of 0.0V and is not included in the PWRGOOD indication.
19. V
SA
has a Vboot setting of 0.9V.
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on final silicon
characterization.
2. I
CC_TDC
(Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing
indefinitely and should be used for the voltage regulator thermal assessment. The voltage regulator is responsible for
monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion.
3. Specification is at T
CASE
= 50 °C. Characterized by design (not tested).
4. I
CCD_01_MAX
and I
CCD_23_MAX
refers only to the processor current draw and does not account for the current consumption by
the memory devices. Memory Standby Current is characterized by design and not tested.
5. Minimum V
CC
and maximum I
CC
are specified at the maximum processor case temperature (T
CASE
). I
CC_MAX
is specified at the
relative V
CC_MAX
point on the V
CC
load line. The processor is capable of drawing I
CC_MAX
for up to 5 seconds. Refer to
Figure 7-3 for further details on the average processor current draw over various time durations.
Table 7-11. Current Specifications
Parameter Symbol and Definition
Processor TDP / Core
Count
TDC (A) Max (A) Notes
1
I
CC
Core Supply, Processor Current on V
CC
130W 6-core, 4-core 135 165 4, 5
I
TT
I/O Termination Supply, Processor Current on
V
TTA
/V
TTD
130W 6-core, 4-core 20 24 4, 5
I
SA
System Agent Supply, Processor Current on
V
SA
130W 6-core, 4-core 20 24 4, 5
I
CCD_01
DDR3 Supply, Processor Current V
CCD_01
130W 6-core, 4-core 3 4 4, 5
I
CCD_23
DDR3 Supply, Processor Current V
CCD_23
130W 6-core, 4-core 3 4 4, 5
I
CCPLL
PLL Supply, Processor Current on V
CCPLL
130W 6-core, 4-core 2 2 4, 5
I
CCD_01_23,
I
CCD_23_23
DDR3 Supply, Current
on V
CCD_01/
V
CCD_23
in System S3 Standby
State
130W 6-core, 4-core — 0.5 4