Datasheet

Electrical Specifications
62 Datasheet
Notes:
1. Refer to Table 7-17 for details on the R
ON
(Buffer on Resistance) value for this signal.
7.3 Power-On Configuration (POC) Options
Several configuration options can be configured by hardware. The processor samples
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, refer to Table 7-7.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed, except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
Notes:
1. Output tri-state option enables Fault Resilient Booting (FRB). The RESET_N signal is used to latch
PROCHOT_N for enabling FRB mode.
2. BIST_ENABLE is sampled at RESET_N de-assertion (on the falling edge).
3. This signal is sampled after PWRGOOD assertion.
7.4 Absolute Maximum and Minimum Ratings
Table 7-8 specifies absolute maximum and minimum ratings. At conditions outside
functional operation condition limits, but within absolute maximum and minimum
ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to
conditions outside these limits, but within the absolute maximum and minimum
ratings, the device may be functional; however, with its lifetime degraded depending on
exposure to conditions exceeding the functional operation condition limits.
Although the processor contains protective circuitry to resist damage from Electro-
Static Discharge (ESD), precautions should always be taken to avoid high static
voltages or electric fields.
Table 7-6. Signals with On-Die Termination
Signal Name
Pull-Up /
Pull-Down
Rail Value Units Notes
DDR{0/1}_PAR_ERR_N Pull-Up VCCD_01 65 Ω
DDR{2/3}_PAR_ERR_N Pul-Up VCCD_23 65 Ω
TXT_AGENT Pull-Down VSS 2K Ω
SAFE_MODE_BOOT Pull-Down VSS 2K Ω
BIST_ENABLE Pul-Up VTT 2K Ω
TXT_PLTEN Pul-Up VTT 2K Ω
EAR_N Pull-Up VTT 2K Ω 1
Table 7-7. Power-On Configuration Option Lands
Configuration Option Land Name Notes
Output tri state PROCHOT_N 1
Execute BIST (Built-In Self Test) BIST_ENABLE 2
Enable Intel
®
Trusted Execution Technology (Intel
®
TXT) Platform TXT_PLTEN 3
Power-up Sequence Halt for ITP configuration EAR_N 3
Enable Intel Trusted Execution Technology (Intel TXT) Agent TXT_AGENT 3
Enable Safe Mode Boot SAFE_MODE_BOOT 3