Datasheet

Datasheet 59
Electrical Specifications
7.1.9 Reserved or Unused Signals
All Reserved (RSVD) signals must not be connected. Connection of these signals to V
CC
,
V
TTA
, V
TTD
, V
CCD,
V
CCPLL
, V
SS
, or to any other signal (including each other) can result in
component malfunction or incompatibility with future processors. See Chapter 8 for a
land listing of the processor and the location of all Reserved (RSVD) signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
SS
). Unused outputs may be left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability.
7.2 Signal Group Summary
Signals are grouped by buffer type and similar characteristics as listed in Table 7-5. The
buffer type indicates which signaling technology and specifications apply to the signals.
Note:
1. Qualifier for a buffer type.
Table 7-4. Signal Description Buffer Types
Signal Description
Analog Analog reference or output. May be used as a threshold voltage or for buffer
compensation
Asynchronous Signal has no timing relationship with any system reference clock.
CMOS CMOS buffers: 1.0V or 1.5V tolerant
DDR3 DDR3 buffers: 1.5V and 1.35V tolerant
DMI2 Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express*
2.0 and 1.0 Signaling Environment AC Specifications.
Open Drain CMOS Open Drain CMOS (ODCMOS) buffers: 1.0V tolerant
PCI Express* PCI Express* interface signals. These signals are compatible with PCI Express 3.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCI Express specification.
Reference Voltage reference signal.
SSTL Source Series Terminated Logic (JEDEC SSTL_15)
Table 7-5. Signal Groups (Sheet 1 of 3)
Differential /
Single Ended
Buffer Type Signals
1
DDR3 Reference Clocks
2
Differential SSTL Output DDR{0/1/2/3}_CLK_D[N/P][3:0]
DDR3 Command Signals
2
Single ended
SSTL Output
DDR{0/1/2/3}_BA[2:0]
DDR{0/1/2/3}_CAS_N
DDR{0/1/2/3}_MA[15:00]
DDR{0/1/2/3}_MA_PAR
DDR{0/1/2/3}_RAS_N
DDR{0/1/2/3}_WE_N
CMOS1.5v Output DDR_RESET_C{01/23}_N