Datasheet

Datasheet 57
Electrical Specifications
reduce the switching frequency or pulse skip, or change to asynchronous regulation.
For example, typical power states are 00h = run in normal mode; a command of
01h= shed phases mode, and an 02h=pulse skip.
The VR may reduce the number of active phases from PS(00h) to PS(01h) or PS(00h)
to PS(02h) for example. There are multiple VR design schemes that can be used to
maintain a greater efficiency in these different power states; work with your VR
controller suppliers for optimizations.
The SetPS command sends a byte that is encoded as to what power state the VR
should transition to.
If a power state is not supported by the controller, the slave should acknowledge with
command rejected (11b).
If the VR is in a low-power state and receives a SetVID command moving the VID up,
the VR exits the low-power state to normal mode (PS0) to move the voltage up as fast
as possible. The processor must re-issue the low-power state (PS1 or PS2) command if
it is in a low-current condition at the new higher voltage. See Figure 7-2 for VR power
state transitions.
7.1.8.3.6 SVID Voltage Rail Addressing
The processor addresses four different voltage rail control segments within VR12 (V
CC
,
V
CCD_01
, V
CCD_23
, and V
SA
). The SVID data packet contains a 4-bit addressing code.
Notes:
1. Check with VR vendors for determining the physical address assignment method for their controllers.
2. VR addressing is assigned on a per voltage rail basis.
Figure 7-2. Voltage Regulator (VR) Power-State Transitions
PS0
PS2PS1
Table 7-2. Serial Voltage Identification (SVID) Address Usage
PWM Address (Hex) Processor
00 V
cc
01 V
sa
02 V
CCD_01
03 +1 not used
04 V
CCD_23
05 +1 not used