Datasheet

Datasheet 5
Figures
1-1 Processor Platform Block Diagram Example.............................................................9
1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) ..................12
2-1 PCI Express* Layering Diagram...........................................................................19
2-2 Packet Flow through the Layers...........................................................................20
4-1 Idle Power Management Breakdown of the Processor Cores.....................................34
4-2 Thread and Core C-State Entry and Exit ...............................................................34
4-3 Package C-State Entry and Exit...........................................................................38
7-1 Input Device Hysteresis .....................................................................................53
7-2 Voltage Regulator (VR) Power-State Transitions ....................................................57
7-3 VCC Overshoot Example Waveform......................................................................66
Tables
1-1 Terminology .....................................................................................................14
1-2 Processor Documents.........................................................................................16
1-3 Public Specifications ..........................................................................................17
4-1 System States ..................................................................................................30
4-2 Package C-State Support....................................................................................31
4-3 Core C-State Support.........................................................................................31
4-4 System Memory Power States.............................................................................32
4-5 DMI2 / PCI Express* Link States .........................................................................32
4-6 G, S and C State Combinations ...........................................................................33
4-7 Coordination of Thread Power States at the Core Level...........................................35
4-8 P_LVLx to MWAIT Conversion..............................................................................35
4-9 Coordination of Core Power States at the Package Level.........................................38
4-10 Package C-State Power Specifications ..................................................................40
6-1 Memory Channel DDR0, DDR1, DDR2, DDR3.........................................................44
6-2 Memory Channel Miscellaneous ...........................................................................45
6-3 PCI Express* Port 1 Signals................................................................................45
6-4 PCI Express* Port 2 Signals................................................................................45
6-5 PCI Express* Port 3 Signals................................................................................46
6-6 PCI Express* Miscellaneous Signals .....................................................................46
6-7 DMI2 and PCI Express Port 0 Signals ...................................................................47
6-8 Platform Environment Control Interface (PECI) Signals...........................................47
6-9 System Reference Clock (BCLK{0/1}) Signals.......................................................47
6-10 Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals ..........................47
6-11 Serial Voltage Identification (SVID) Signals...........................................................48
6-12 Processor Asynchronous Sideband Signals ............................................................48
6-13 Miscellaneous Signals ........................................................................................50
6-14 Power and Ground Signals..................................................................................51
7-1 Power and Ground Lands....................................................................................54
7-2 Serial Voltage Identification (SVID) Address Usage ................................................57
7-3 VR12.0 Reference Code Voltage Identification (VID) Table ......................................58
7-4 Signal Description Buffer Types...........................................................................59
7-5 Signal Groups...................................................................................................59
7-6 Signals with On-Die Termination .........................................................................62
7-7 Power-On Configuration Option Lands ..................................................................62
7-8 Processor Absolute Minimum and Maximum Ratings...............................................63
7-9 Storage Condition Ratings ..................................................................................63