Datasheet

ManualsBrandsIntel Manualscomputer componentsCL8064701528402

329366-002

Intel

Core™ i7 Processor Family for

LGA2011 Socket

Datasheet – Volume 1 of 2

Supporting Desktop Intel

Core™ i7-4960X Extreme Edition Processor

Series for the LGA2011 Socket

Supporting Desktop Intel

Core™ i7-49xx and i7-48xx Processor Series

for the LGA2011 Socket

May 2014

Summary of content (116 pages)

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Intel® Core™ i7 Processor Family for LGA2011 Socket Datasheet – Volume 1 of 2 Supporting Desktop Intel® Core™ i7-4960X Extreme Edition Processor Series for the LGA2011 Socket Supporting Desktop Intel® Core™ i7-49xx and i7-48xx Processor Series for the LGA2011 Socket May 2014 329366-002
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By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below. INFORMATION SALE AND/OR USE IN THIS OF INTEL DOCUMENT PRODUCTS IS PROVIDED INCLUDING IN CONNECTION LIABILITY OR WITH WARRANTIES Intel® PRODUCTS. RELATING TO NO FITNESS LICENSE,FOR Express* A PARTICULAR OR IMPLIED, PURPOSE, BY ESTOPPEL MERCHANTABILITY, OR OTHERWISE, OR INFRINGEMENT TO ANY INTELLECTUAL OF ANY PROPERTY PATENT, COPYRIGHT RIGHTS ISOR GRANTED OTHER INTELLECTUAL BY THIS DOCUMENT.
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Table of Contents 1 Introduction .............................................................................................................. 8 1.1 Processor Feature Details ..................................................................................... 9 1.2 Supported Technologies ..................................................................................... 10 1.3 Interfaces ........................................................................................................ 10 1.3.
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.2 4.3 4.4 Processor Core / Package Power Management .......................................................33 4.2.1 Enhanced Intel® SpeedStep® Technology ..................................................33 4.2.2 Low-Power Idle States.............................................................................34 4.2.3 Requesting Low-Power Idle States ............................................................35 4.2.4 Core C-states .......................................................................
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Figures 1-1 1-2 2-1 2-2 4-1 4-2 4-3 7-1 7-2 7-3 Processor Platform Block Diagram Example............................................................. 9 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) .................. 12 PCI Express* Layering Diagram........................................................................... 19 Packet Flow through the Layers...........................................................................
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7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 8-1 8-2 6 Voltage Specifications.........................................................................................64 Current Specifications ........................................................................................65 VCC Overshoot Specifications ..............................................................................66 DDR3 and DDR3L Signal DC Specifications ............................................................
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Revision History Revision Number 001 002 Description • Initial release • Chapter , "1 Introduction 9," — Section 1.3.
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Introduction 1 Introduction The Intel® Core™ i7 processor family for LGA2011 socket are the next generation of 64-bit, multi-core desktop processors built on 22-nanometer process technology. Based on the low-power/high-performance Intel® Core™ i7 processor micro-architecture, the processor is designed for a two-chip platform instead of to the traditional three-chip platforms (processor, Memory Controller Hub, and Platform Controller Hub).
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Introduction DDR3 DDR3 DDR3 Processor Platform Block Diagram Example DDR3 Figure 1-1. ethernet SATA Processor BIOS PCIe* DMI2 PCIe* PCH PCIe* x4 PCIe* ... x1 PCIe* x16 x16 x8 1.
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Introduction 1.2 Supported Technologies • Intel® Virtualization Technology (Intel® VT) • Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) • Intel® Virtualization Technology (Intel® VT) Processor Extensions • Intel® 64 Architecture • Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1) • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.
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Introduction 1.3.2 PCI Express* • The PCI Express* port(s) are fully-compliant with the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0) • Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) • Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports • 4 lanes of PCI Express* at PCIe* 2.
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Introduction Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) Port 0 DMI / PCIe Transaction Port 1 (IOU2) PCIe Port 2 (IOU0) PCIe Transaction Port 3 (IOU1) PCIe Transaction Transaction Link Link Link Link Physical Physical Physical Physical 0…3 0…3 4…7 0…3 4…7 8…11 12..15 0…3 4…7 8…11 12..
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Introduction 1.3.4 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH). Refer to the Processor Thermal Mechanical Specifications and Design Guide for additional details on PECI services available in the processor (Refer to the Related Documents section).
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Introduction 1.6 Package Summary The processor socket type is noted as LGA2011. The processor package is a 52.5 x 45 mm FC-LGA package (LGA2011). Refer to the Processor Thermal Mechanical Specification and Design Guide (see Related Documents section) for the package mechanical specifications. 1.7 Terminology Table 1-1.
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Introduction Table 1-1. Terminology (Sheet 2 of 3) Term Datasheet Description Intel® VT-d Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a hardware assist, under system software (Virtual Machine Manager or operating system) control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d.
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Introduction Table 1-1. Terminology (Sheet 3 of 3) Term Uncore Unit Interval Description The portion of the processor comprising the shared cache, IMC, HA, PCU, and UBox. Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t1, t2, tn,...., tk then the UI at instance “n” is defined as: UI 1.
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Introduction Table 1-3. Public Specifications Document Document Number / Location Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info PCI Local Bus Specification 3.0 http://www.pcisig.com/specifications PCI Express Base Specification - Revision 2.1 and 1.1 PCI Express Base Specification - Revision 3.0 http://www.pcisig.com System Management Bus (SMBus) Specification, Revision 2.0 http://smbus.org/ DDR3 SDRAM Specification http://www.jedec.
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Interfaces 2 Interfaces This chapter describes the functional behaviors supported by the processor. Topics covered include: • System Memory Interface • PCI Express* Interface • Direct Media Interface 2 (DMI2) / PCI Express* Interface • Platform Environment Control Interface (PECI) 2.1 System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels and supports 1 unbuffered DIMM per channel. 2.1.
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Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.
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Interfaces Figure 2-2. Packet Flow through the Layers Framing Sequence Number Header Date ECRC LCRC Framing Transaction Layer Data Link Layer Physical Layer 2.2.1.1 Transaction Layer The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events.
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Interfaces region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express* configuration access mechanism described in the PCI Express* Enhanced Configuration Mechanism section. The PCI Express* Host Bridge is required to translate the memory-mapped PCI Express* configuration space accesses from the host processor to PCI Express* configuration cycles.
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Interfaces The interface design was optimized for interfacing to Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components.
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Technologies 3 Technologies This chapter covers the following technologies: • Intel® Virtualization Technology (Intel® VT) • Security Technologies • Intel® Hyper-Threading Technology (Intel® HT Technology) • Intel® Turbo Boost Technology • Enhanced Intel® SpeedStep® Technology • Intel® Advanced Vector Extensions (Intel® AVX) 3.1 Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software.
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Technologies 3.1.2 Intel® VT-x Features The processor core supports the following Intel VT-x features: • Extended Page Tables (EPT) — hardware assisted page table virtualization. — eliminates VM exits from guest operating system to the VMM for shadow pagetable maintenance. • Virtual Processor IDs (VPID) — Ability to assign a VM ID to tag processor core hardware structures (such as, TLBs).
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Technologies 3.1.3.
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Technologies 3.2 Security Technologies 3.2.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Instructions These instructions enable fast and secure data encryption and decryption, using the Advanced Encryption Standard (Intel AES-NI) which is defined by FIPS Publication number 197. Since Intel AES-NI is the dominant block cipher, and it is deployed in various protocols, the new instructions will be valuable for a wide range of applications.
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Technologies 3.4 Intel® Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits. The result is increased performance in multithreaded and single threaded workloads. It should be enabled in the BIOS for the processor to operate with maximum performance. 3.4.
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Technologies 3.6 Intel® Advanced Vector Extensions (Intel® AVX) Intel Advanced Vector Extensions (Intel AVX) is a new 256-bit vector SIMD extension of Intel Architecture. The introduction of Intel AVX started with the 2nd Generation Intel® Core™ processor family. Intel AVX accelerates the trend of parallel computation in general purpose applications like image, video and audio processing, engineering applications (such as 3D modeling and analysis), scientific simulation, and financial analysts.
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Technologies • Compatibility – Intel AVX is backward compatible with previous ISA extensions including Intel SSE4: — Existing Intel SSE applications/library can: • Run unmodified and benefit from processor enhancements • Recompile existing Intel® SSE intrinsic using compilers that generate Intel AVX code • Inter-operate with library ported to Intel AVX — Applications compiled with Intel AVX can inter-operate with existing Intel SSE libraries.
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Power Management 4 Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States Supported • Processor Core / Package Power Management • System Memory Power Management • Direct Media Interface 2 (DMI2) / PCI Express* Power Management 4.1 Advanced Configuration and Power Interface (ACPI) States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1.
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Power Management Table 4-2.
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Power Management 4.1.3 Integrated Memory Controller (IMC) States Table 4-4. System Memory Power States State Description Power Up/Normal Operation CKE asserted. Active Mode, highest power consumption. CKE Power Down Opportunistic, per rank control after idle time: • Active Power Down (APD) (default mode) — CKE de-asserted. Power savings in this mode, relative to active idle state is about 55% of the memory power. Exiting this mode takes 3 – 5 DCLK cycles.
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Power Management 4.1.5 G, S, and C State Combinations Table 4-6. G, S and C State Combinations 4.
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Power Management 4.2.2 Low-Power Idle States When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-States. However, higher C-states have longer exit and entry latencies. Resolution of C-states occurs at the thread, processor core, and processor package level. Thread level C-states are available if Intel Hyper-Threading Technology is enabled.
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Power Management Table 4-7. Coordination of Thread Power States at the Core Level Processor Core C-State Thread 0 Thread 1 C0 C1 C3 C6 C7 C0 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C11 C3 C0 C11 C3 C3 C3 C6 C0 C11 C3 C6 C6 C7 C0 C11 C3 C6 C7 Note: 1. If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher. 4.2.
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Power Management 4.2.4 Core C-states The following are general rules for all core C-states, unless specified otherwise: • A core C-state is determined by the lowest numerical thread state (such as, Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See Table 4-6. • A core transitions to C0 state when: — an interrupt occurs. — there is an access to the monitored address if the state was entered using an MWAIT instruction.
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Power Management 4.2.4.6 Delayed Deep C-States The Delayed Deep C-states (DDCst) feature on this processor replaces the “C-state auto-demotion” scheme used in the previous processor generation. Deep C-states are defined as CC3 through CC7 (refer to Table 4-3 for supported deep C-states).
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Power Management There is also a concept of Execution Allowed (EA). When EA status is 0, the cores in a socket are in C3 or a deeper state; a socket initiates a request to enter a coordinated package C-state. The coordination is across all sockets and the PCH. Table 4-9 shows an example of a dual-core processor package C-state resolution. Figure 4-3 summarizes package C-state transitions with package C2 as the interim between PC0 and PC1 prior to PC3 and PC6. Table 4-9.
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Power Management 4.2.5.2 Package C1/C1E State No additional power reduction actions are taken in the package C1 state. However, if the C1E substate is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. Autonomous power reduction actions that are based on idle timers, can trigger depending on the activity in the system. The package enters the C1 low-power state when: • At least one core is in the C1 state.
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Power Management 4.2.5.5 Package C6 State A processor enters the package C6 low-power state when: • At least one core is in the C6 state. • The other cores are in a C6 or lower power state, and the processor has been granted permission by the platform. • L3 shared cache retains context and becomes inaccessible in this state.
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Power Management 4.3.1 CKE Power-Down The CKE input land is used to enter and exit different power-down modes. The memory controller has a configurable activity timeout for each rank. When no reads are present to a given rank for the configured interval, the memory controller will transition the rank to power-down mode. The memory controller transitions the DRAM to power-down by de-asserting CKE and driving a NOP command.
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Power Management 4.3.2.2 Self-Refresh Exit Self-refresh exit can be either a message from an external unit (PCU in most cases, but also possibly from any message-channel master) or as reaction for an incoming transaction. Here are the proper actions on self-refresh exit: • CK is enabled, and four CK cycles driven. • When proper skew between Address/Command and CK are established, assert CKE. • Issue NOPs for tXSRD cycles. • Issue ZQCL to each rank. • The global scheduler will be enabled to issue commands.
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Thermal Management Specifications 5 Thermal Management Specifications The processor requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete solution includes both component and system-level thermal management features.
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Signal Descriptions 6 Signal Descriptions This chapter describes the processor signals. The signals are arranged in functional groups according to their associated interface or category. 6.1 System Memory Interface Signals Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3 Signal Name 44 Description DDR{0/1/2/3}_BA[2:0] Bank Address: These signals define the bank which is the destination for the current Activate, Read, Write, or PRECHARGE command.
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Signal Descriptions Table 6-2. Memory Channel Miscellaneous Signal Name Description DDR_RESET_C01_N DDR_RESET_C23_N System Memory Reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while DDR_RESET_C23_N is used for memory channels 2 and 3. DDR_SCL_C01 DDR_SCL_C23 SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs.
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Signal Descriptions Table 6-4. PCI Express* Port 2 Signals (Sheet 2 of 2) Signal Name Table 6-5. Description PE2C_TX_DN[11:8] PE2C_TX_DP[11:8] PCIe Transmit Data Output PE2D_TX_DN[15:12] PE2D_TX_DP[15:12] PCIe Transmit Data Output PCI Express* Port 3 Signals Signal Name Table 6-6.
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Signal Descriptions 6.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Port 0 Signals Table 6-7. DMI2 and PCI Express Port 0 Signals Signal Name Description DMI_RX_DN[3:0] DMI_RX_DP[3:0] DMI2 Receive Data Input DMI_TX_DP[3:0] DMI_TX_DN[3:0] DMI2 Transmit Data Output 6.4 Platform Environment Control Interface (PECI) Signal Table 6-8.
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Signal Descriptions Table 6-10. Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals (Sheet 2 of 2) Signal Name 6.7 Description TMS Test Mode Select: This signal is a JTAG specification support signal used by debug tools. TRST_N Test Reset: This signal resets the Test Access Port (TAP) logic. TRST_N must be driven low during power on Reset. Serial Voltage Identification (SVID) Signals Table 6-11. Serial Voltage Identification (SVID) Signals Signal Name 6.
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Signal Descriptions Table 6-12. Processor Asynchronous Sideband Signals (Sheet 2 of 3) Signal Name PROCHOT_N PWRGOOD Description Processor Hot: PROCHOT_N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal can also be driven to the processor to activate the Thermal Control Circuit.
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Signal Descriptions Table 6-12. Processor Asynchronous Sideband Signals (Sheet 3 of 3) Signal Name Description Intel® TXT_AGENT Trusted Execution Technology (Intel® TXT) Agent: This is a strap signal: 0 = Default. The socket is not the Intel® TXT Agent. 1 = The socket is the Intel® TXT Agent. In non-Scalable dual-processor (DP) platforms, the legacy socket (identified by SOCKET_ID[1:0] = 00b) with Intel TXT Agent should always set the TXT_AGENT to 1b.
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Signal Descriptions 6.9 Processor Power and Ground Supplies Table 6-14. Power and Ground Signals Signal Name VCC Description Variable power supply for the processor cores, lowest level caches (LLC), ring interface, and home agent. It is provided by a VRM/EVRD 12.0 compliant regulator for each processor socket. The output voltage of this supply is selected by the processor, using the serial voltage ID (SVID) bus. Note: VCC has a Vboot setting of 0.0 V and is not included in the PWRGOOD indication.
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Electrical Specifications 7 Electrical Specifications This chapter covers the following topics: • Processor Signaling • Signal Group Summary • Power-On Configuration (POC) Options • Absolute Maximum and Minimum Ratings • DC Specifications 7.1 Processor Signaling The processor includes 2011 lands that use various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups.
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Electrical Specifications 7.1.4 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
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Electrical Specifications Clock multiplying within the processor is provided by the internal phase locked loop (PLL) that requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP, BCLK{0/1}_DN inputs are provided in Table 7-15. 7.1.5.1 PLL Power Supply An on-die PLL filter solution is implemented on the processor. Refer to Table 7-10 for DC specifications. 7.1.
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Electrical Specifications Table 7-1. 7.1.8.2 Power and Ground Lands (Sheet 2 of 2) Power and Ground Lands Number of Lands Comments VCCD_01 VCCD_23 51 Each VCCD land is connected to a switchable 1.50V and 1.35V supply to provide power to the processor DDR3 interface. These supplies also power the DDR3 memory subsystem. VCCD is also controlled by the SVID Bus. VCCD is the generic term for VCCD_01, VCCD_23. VTTA 14 VTTA lands must be supplied by a fixed 1.0V supply.
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Electrical Specifications • SetVID_slow (5mV/µs for VCC, 2.5mV/µs for VSA/VCCD), and • Slew Rate Decay (downward voltage only and it is a function of the output capacitance time constant) commands. Table 7-3 includes SVID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 7-10. The VRM or EVRD used must be capable of regulating its output to the value defined by the new VID.
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Electrical Specifications reduce the switching frequency or pulse skip, or change to asynchronous regulation. For example, typical power states are 00h = run in normal mode; a command of 01h= shed phases mode, and an 02h=pulse skip. The VR may reduce the number of active phases from PS(00h) to PS(01h) or PS(00h) to PS(02h) for example.
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Electrical Specifications 3. 4. Table 7-3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase count. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not used. VR12.0 Reference Code Voltage Identification (VID) Table Hex VCC, VSA, VCCD Hex VCC, VSA, VCCD Hex VCC, VSA, VCCD VCC, VSA, VCCD Hex 00 0.00000 55 0.67000 78 0.84500 33 0.50000 56 0.67500 79 0.85000 9B 1.02000 BE 1.
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Electrical Specifications 7.1.9 Reserved or Unused Signals All Reserved (RSVD) signals must not be connected. Connection of these signals to VCC, VTTA, VTTD, VCCD, VCCPLL, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 8 for a land listing of the processor and the location of all Reserved (RSVD) signals.
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Electrical Specifications Table 7-5. Signal Groups (Sheet 2 of 3) Differential / Single Ended Signals1 Buffer Type DDR3 Control Signals2 CMOS1.
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Electrical Specifications Table 7-5. Signal Groups (Sheet 3 of 3) Differential / Single Ended Single ended Signals1 Buffer Type Open Drain CMOS Input/Output DDR_SCL_C{01/23} DDR_SDA_C{01/23} PEHPSCL PEHPSDA JTAG and TAP Signals CMOS1.0v Input Single ended TCK, TDI, TMS, TRST_N CMOS1.0v Input/Output PREQ_N CMOS1.0v Output PRDY_N Open Drain CMOS Input/Output BPM_N[7:0] EAR_N Open Drain CMOS Output TDO Serial VID Interface (SVID) Signals Single ended CMOS1.
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Electrical Specifications Table 7-6. Signals with On-Die Termination Signal Name DDR{0/1}_PAR_ERR_N DDR{2/3}_PAR_ERR_N Pull-Up / Pull-Down Rail Value Units Pull-Up VCCD_01 65 Ω Pul-Up VCCD_23 65 Ω TXT_AGENT Pull-Down VSS 2K Ω SAFE_MODE_BOOT Pull-Down VSS 2K Ω Pul-Up VTT 2K Ω TXT_PLTEN Pul-Up VTT 2K Ω EAR_N Pull-Up VTT 2K Ω BIST_ENABLE Notes 1 Notes: 1. Refer to Table 7-17 for details on the RON (Buffer on Resistance) value for this signal. 7.
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Electrical Specifications Table 7-8. Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit VCC Processor core voltage with respect to VSS -0.3 1.4 V VCCPLL Processor PLL voltage with respect to VSS -0.3 2.0 V VCCD Processor I/O supply voltage for DDR3 (standard voltage) with respect to VSS -0.3 1.85 V VCCD Processor I/O supply voltage for DDR3L (low Voltage) with respect to VSS -0.3 1.7 V VSA Processor SA voltage with respect to VSS -0.3 1.
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Electrical Specifications 2. 3. 4. 5. 7.5 These ratings apply to the Intel component and do not include the tray or packaging. Failure to adhere to this specification can affect the long-term reliability of the processor. Non-operating storage limits post board attach: Storage condition limits for the component once attached to the application board are not specified.
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Electrical Specifications 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. The VTTA, and VTTD voltage specification requirements are measured across the remote sense pin pairs (VTTD_SENSE and VSS_VTTD_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance.
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Electrical Specifications 7.5.2 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 7-12 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. 7.5.2.
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Electrical Specifications 7.5.3 Signal DC Specifications DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each specification. Table 7-13. DDR3 and DDR3L Signal DC Specifications Symbol IIL Parameter Input Leakage Current Min Typ Max Units Notes1 -1.4 — +1.
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Electrical Specifications 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. The voltage rail VCCD which will be set to 1.50V or 1.35V nominal depending on the voltage of all DIMMs connected to the processor. VIL is the maximum voltage level at a receiving agent that will be interpreted as a logical low value. VIH is the minimum voltage level at a receiving agent that will be interpreted as a logical high value. VIH and VOH may experience excursions above VCCD.
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Electrical Specifications 4. 5. 6. 7. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. VHavg can be measured directly using “Vtop” on Agilent* and “High” on Tektronix oscilloscopes. VCROSS is defined as the total variation of all crossing voltages as defined in Note 3. The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP. For Vin between 0 and VIH. Table 7-16.
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Electrical Specifications 1. 2. 3. 4. 5. VTT refers to instantaneous VTT. Measured at 0.31*VTT Vin between 0V and VTT These are measured between VIL and VIH. The signal edge rate must be met or the signal must transition monotonically to the asserted state. Table 7-19. Processor Asynchronous Sideband DC Specifications Symbol Parameter Min Max Units Notes CMOS1.0v Signals VIL_CMOS1.0v Input Low Voltage — 0.3*VTT V 1, 2 VIH_CMOS1.0v Input High Voltage 0.
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Electrical Specifications 7.5.3.1 PCI Express* DC Specifications The processor DC specifications for the PCI Express* are available in the PCI Express Base Specification, Revision 3.0. This document will provide only the processor exceptions to the PCI Express Base Specification, Revision 3.0. 7.5.3.2 DMI2/PCI Express* DC Specifications The processor DC specifications for the DMI2/PCI Express* are available in the PCI Express Base Specification, Revisions 2.0 and 1.0.
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Processor Land Listing 8 Processor Land Listing This chapter provides the processor land lists. Table 8-1 is a listing of all processor lands ordered alphabetically by land name. Table 8-2 is a listing of all processor lands ordered by land number.
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Processor Land Listing Table 8-1. Land List by Land Name (Sheet 1 of 42) Land No. Buffer Type Direction BCLK0_DN CM44 CMOS I BCLK0_DP CN43 CMOS I BCLK1_DN BA45 CMOS BCLK1_DP AW45 BIST_ENABLE AT48 BPM_N[0] AR43 BPM_N[1] Land List by Land Name (Sheet 2 of 42) Land No.
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Processor Land Listing Table 8-1. Land List by Land Name (Sheet 3 of 42) Land Name Datasheet Land No. Buffer Type Table 8-1. Direction Land Name Land List by Land Name (Sheet 4 of 42) Land No.
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Processor Land Listing Table 8-1. Land List by Land Name (Sheet 5 of 42) Land List by Land Name (Sheet 6 of 42) Land No.
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Processor Land Listing Table 8-1. Land List by Land Name (Sheet 7 of 42) Land No. Buffer Type Direction Land Name DDR1_DQ[50] CR41 SSTL I/O DDR1_DQ[51] CU41 SSTL I/O DDR1_DQ[52] CT36 SSTL DDR1_DQ[53] CV36 DDR1_DQ[54] CT40 DDR1_DQ[55] CV40 DDR1_DQ[56] DE37 Land Name Datasheet Table 8-1. Land List by Land Name (Sheet 8 of 42) Land No.
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Processor Land Listing Table 8-1. Land List by Land Name (Sheet 9 of 42) Land No. Buffer Type Direction DDR2_CLK_DN[2] W21 SSTL O DDR2_CLK_DN[3] W23 SSTL O DDR2_CLK_DP[0] AB24 SSTL DDR2_CLK_DP[1] AB22 DDR2_CLK_DP[2] AA21 DDR2_CLK_DP[3] AA23 DDR2_CS_N[0] AB20 Land Name 77 Table 8-1. Land List by Land Name (Sheet 10 of 42) Land No.
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Processor Land Listing Table 8-1. Datasheet Land List by Land Name (Sheet 11 of 42) Buffer Type Table 8-1. Land List by Land Name (Sheet 12 of 42) Land Name Land No.
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Processor Land Listing Table 8-1. Table 8-1. Land List by Land Name (Sheet 14 of 42) Land No. Buffer Type Direction DDR3_DQ[03] E37 SSTL I/O DDR3_DQ[47] M10 SSTL I/O DDR3_DQ[04] F40 SSTL I/O DDR3_DQ[48] E7 SSTL I/O DDR3_DQ[05] D40 SSTL I/O DDR3_DQ[49] F6 SSTL I/O Land Name 79 Land List by Land Name (Sheet 13 of 42) Land Name Land No.
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Processor Land Listing Table 8-1. Land List by Land Name (Sheet 15 of 42) Land No. Buffer Type Direction DDR3_DQS_DP[09] E39 SSTL I/O DDR3_DQS_DP[10] M38 SSTL I/O DDR3_DQS_DP[11] D34 SSTL DDR3_DQS_DP[12] N31 DDR3_DQS_DP[13] E11 DDR3_DQS_DP[14] K12 DDR3_DQS_DP[15] G7 Land Name Datasheet Table 8-1. Land List by Land Name (Sheet 16 of 42) Land No.
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Processor Land Listing Table 8-1. Table 8-1. Land List by Land Name (Sheet 18 of 42) Land No.
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Processor Land Listing Table 8-1. Land Name Datasheet Land List by Land Name (Sheet 19 of 42) Land No. Buffer Type Direction Table 8-1. Land Name Land List by Land Name (Sheet 20 of 42) Land No.
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Processor Land Listing Table 8-1. Land List by Land Name (Sheet 21 of 42) Land Name Buffer Type Direction Land Name Land List by Land Name (Sheet 22 of 42) Land No.
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Processor Land Listing Table 8-1. Land No. Buffer Type VCC AN3 PWR VCC AN5 PWR VCC AN7 Land Name Datasheet Land List by Land Name (Sheet 23 of 42) Table 8-1. Land List by Land Name (Sheet 24 of 42) Land No.
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Processor Land Listing Table 8-1. Land Name 85 Land List by Land Name (Sheet 25 of 42) Land No. Buffer Type Direction Table 8-1. Land Name Land List by Land Name (Sheet 26 of 42) Land No.
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Processor Land Listing Table 8-1. Land Name Datasheet Land List by Land Name (Sheet 27 of 42) Land No. Buffer Type Direction O Table 8-1. Land Name Land List by Land Name (Sheet 28 of 42) Land No.
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Processor Land Listing Table 8-1. Land No. Buffer Type VSS A7 GND VSS AA11 GND VSS AA29 VSS VSS VSS VSS VSS VSS Table 8-1. Land List by Land Name (Sheet 30 of 42) Land No.
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Processor Land Listing Table 8-1. Land No. Buffer Type VSS AT12 GND VSS AT14 GND VSS AT16 VSS VSS Table 8-1. Land List by Land Name (Sheet 32 of 42) Land No.
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Processor Land Listing Table 8-1. Land No. Buffer Type VSS BR57 GND VSS BT46 GND VSS BT48 VSS VSS Table 8-1. Land List by Land Name (Sheet 34 of 42) Land No.
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Processor Land Listing Table 8-1. Land No. Buffer Type VSS CH48 GND VSS CH50 GND VSS CH52 VSS VSS Table 8-1. Land List by Land Name (Sheet 36 of 42) Land No.
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Processor Land Listing Table 8-1. Land No. Buffer Type VSS CW35 GND VSS CW37 GND VSS CW39 Land Name 91 Land List by Land Name (Sheet 37 of 42) Table 8-1. Land List by Land Name (Sheet 38 of 42) Land No.
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Processor Land Listing Table 8-1. Land No. Buffer Type VSS H34 GND VSS H38 GND VSS H40 VSS VSS Table 8-1. Land List by Land Name (Sheet 40 of 42) Land No.
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Processor Land Listing Table 8-1. Land List by Land Name (Sheet 41 of 42) Land List by Land Name (Sheet 42 of 42) Land No. Buffer Type VSS W51 GND VTTD BV42 PWR VSS W53 GND VTTD BY20 PWR VSS W9 GND VTTD BY22 PWR VSS Y10 GND VTTD CA21 PWR VSS Y12 GND VTTD CA23 PWR VSS Y28 GND VTTD_SENSE BP42 VSS Y30 GND VSS Y32 GND VSS Y36 GND VSS Y38 GND VSS Y40 GND VSS Y42 GND VSS Y56 GND VSS_VCC_SENSE BY2 O VSS_VSA_SENSE AF14 O Land Name 93 Table 8-1.
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Processor Land Listing Table 8-2. Land No. Land Name Table 8-2. Buffer Type Direction Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Table 8-2. Buffer Type Direction Land No. Land List by Land Number (Sheet 4 of 42) Land Name Buffer Type Direction SSTL O CMOS1.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Direction Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Direction Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Table 8-2. Land List by Land Number (Sheet 10 of Buffer Type Direction Land No.
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Processor Land Listing Table 8-2. Land No. Table 8-2. Buffer Type B38 DDR3_DQS_DN[00] SSTL I/O BB8 VCC PWR B40 DDR3_DQ[00] SSTL I/O BC1 VSS GND B42 DMI_TX_DP[0] PCIEX O BC11 VSS GND B44 DMI_TX_DP[2] PCIEX O BC13 VSS GND B46 RSVD BC15 VSS GND B48 DMI_RX_DP[1] PCIEX I BC17 VSS GND B50 DMI_RX_DP[3] PCIEX I BC3 VSS GND B52 VSS GND BC43 VSS GND B54 VSA PWR BC45 VSS GND B6 VSS GND BC47 RSVD B8 VSS GND BC5 Direction Land No.
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Processor Land Listing Table 8-2. Land No. Datasheet Land List by Land Number (Sheet 13 of Land Name Buffer Type Direction Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Direction Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Direction Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. CB2 Land Name DDR0_DQ[08] Table 8-2. Buffer Type Direction Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Direction Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. CJ5 CJ51 CJ7 Land Name Buffer Type Direction I/O DDR0_DQ[11] SSTL VSS GND DDR0_DQ[06] SSTL I/O Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Direction Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Table 8-2. Direction Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Table 8-2. Direction Land No.
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Processor Land Listing Table 8-2. 109 Land List by Land Number (Sheet 31 of Table 8-2. Land No. Land Name Buffer Type Direction Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Table 8-2. Direction Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Table 8-2. Buffer Type Direction Land No. I/O Land List by Land Number (Sheet 36 of Land Name Buffer Type Direction J37 DDR3_DQS_DP[01] SSTL L11 DDR3_DQS_DN[05] SSTL I/O J39 VSS GND L13 DDR3_DQ[41] SSTL I/O J41 VSS GND L15 PE1A_TX_DP[1] PCIEX3 O CMOS1.
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Processor Land Listing Table 8-2. Land No. Land Name Buffer Type Table 8-2. Direction Land No.
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Processor Land Listing Table 8-2. Land No. R49 R5 R51 Land Name PE3B_TX_DP[7] VSS PE3B_TX_DP[5] Buffer Type Direction PCIEX3 O GND Table 8-2. Land No.
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Processor Land Listing Table 8-2. Land No. Land Name Table 8-2. Buffer Type Direction Land No.
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Package Mechanical Specifications 9 Package Mechanical Specifications The processor is in a Flip-Chip Land Grid Array (FCLGA12) package that interfaces with the baseboard using an LGA2011-0 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
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Boxed Processor Specifications 10 Boxed Processor Specifications 10.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The processors (LGA2011-0) are offered as Intel boxed processors; however, the thermal solutions is sold separately. Boxed processors do not include a thermal solution in the box. Intel offers boxed thermal solutions separately through the same distribution channels.