Manualshelf

Specification Update

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 950 MHz, 128K Cache, 100 MHz FSB
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Errata
34 Specification Update
AM46 IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
Problem: The IO_SMI bit in SMRAM's location 7FA4H is set to "1" by the CPU to indicate a
System Management Interrupt (SMI) occurred as the result of executing an instruction
that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly
set by:
• A non-I/O instruction.
• SMI is pending while a lower priority event interrupts.
• A REP I/O read.
• An I/O read that redirects to MWAIT.
Implication: SMM handlers may get false IO_SMI indication.
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was
triggered by an instruction that read from an I/O port. The SMM handler must not
restart an I/O instruction if the platform has not been configured to generate a
synchronous SMI for the recorded I/O port address.
Status: For the steppings affected, see the Summary Tables of Changes.
AM47 INIT Does Not Clear Global Entries in the TLB
Problem: INIT may not flush a TLB entry when:
• The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register).
• G bit for the page table entry is set.
• TLB entry is present in TLB when INIT occurs.
Implication: Software may encounter unexpected page fault or incorrect address translation due to
a TLB entry erroneously left in TLB after INIT.
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE)
registers before writing to memory early in BIOS code to clear all the global entries
from TLB.
Status: For the steppings affected, see the Summary Tables of Changes.
AM48 Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
Problem: Memory type aliasing occurs when a single physical page is mapped to two or more
different linear addresses, each with different memory type. Memory type aliasing
with the memory types WB and WT may cause the processor to perform incorrect
operations leading to unpredictable behavior.
Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable
behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.