Guide

Platform Design Checklist
R
Intel
®
852GM Chipset Platform Design Guide 253
Pin Name System
Pull-up/Pull-down
Notes
9
DVOBD[11:0]
DVOBCLK
DVOBCLK#
DVOBHSYNC
DVOBVSYNC
DVOBBLANK#
Intel 852GM GMCH supports only one DVO port.
So, these signals should be left as NC.
DVOBFLDSTL
(pin M2)
100 k
Ω pull-down to gnd
For Intel 852GM GMCH, pull-down resistor
required on this signal (10 k-100 k).
MI2CCLK,
MI2CDATA
2.2 k
Ω pull-up to Vcc1_5
Pull-up resistor required on each signal even if
they are unused (2.2 k-100 k). This signal is 1.5 V
tolerant. It may require voltage translation circuit.
MDVICLK,
MDVIDATA
2.2 k
Ω pull-up to Vcc1_5
Pull-up resistor required on each signal even if
they are unused (2.2 k-100 k). This signal is 1.5 V
tolerant. It may require voltage translation circuit.
MDDCCLK,
MDDCDATA
2.2 k
Ω pull-up to Vcc1_5
Pull-up resistor required on each signal even if
they are unused (2.2 k-100 k). This signal is 1.5 V
tolerant. It may require voltage translation circuit.
ADDID[6:0] Leave as NC.
ADDID7
1 k
Ω pull-down to gnd if DVO
device is onboard
If DVO interface is not used, this signal can be left
as “no connect”. Otherwise, pull-down is needed.
DVODETECT
1 k
Ω pull-up to Vcc1_5
if DVO interface is unused
If DVO interface is used, leave as NC. This signal
has internal pull-down.
DPMS Connect to 1.5 V version of ICH4-M’s SUSCLK or
a clock that runs during S1.
See Figure 143.
Figure 143. DPMS Clock Implementation
From
ICH4-M
SUSCLK
BSS138
3
1
2
1K
PM_SUS_ CLK
Vcc1_5
SUS_CLK
To G MC H
DPMS pin