Guide

R
Intel
®
852GM Chipset Platform Design Guide 13
Figure 100. Termination Plane .............................................................................................. 187
Figure 101. Intel 82562ET/EM Disable Circuitry ................................................................... 188
Figure 102. Trace Routing..................................................................................................... 189
Figure 103. Ground Plane Separation................................................................................... 191
Figure 104. RTC Power Well Isolation Control ..................................................................... 194
Figure 105. ICH4-M CPU CMOS Signals with CPU and FWH ............................................. 195
Figure 106. Clock Distribution Diagram................................................................................. 198
Figure 107. Source Shunt Termination Topology ................................................................. 199
Figure 108. CLK66 Clock Group Topology ........................................................................... 202
Figure 109. CLK33 Group Topology ..................................................................................... 203
Figure 110. PCI Clock Group Topology ................................................................................ 204
Figure 111. CLK14 Clock Group Topology ........................................................................... 205
Figure 112. DOTCLK Clock Topology................................................................................... 206
Figure 113. SSCCLK Clock Topology ................................................................................... 207
Figure 114. USBCLK Clock Topology ................................................................................... 208
Figure 115. Platform Power Delivery Map............................................................................. 212
Figure 116. Platform Power Delivery Map for Intel Celeron M Processor ............................ 213
Figure 117. GMCH Power-Up Sequence .............................................................................. 216
Figure 118. ICH4-M Power-Up Sequence............................................................................. 217
Figure 119. Example V
5REF
/ V
5REFSUS
Sequencing Circuitry.................................................. 219
Figure 120. V5REFSUS With +V5ALWAYS Connection Option .......................................... 219
Figure 121. V5REFSUS With +V3ALWAYS and +V5S or +V5 Connection Option.............. 220
Figure 122. Example for Minimizing Loop Inductance .......................................................... 221
Figure 123. DDR Power Delivery Block Diagram.................................................................. 224
Figure 124. GMCH SMRCOMP Resistive Compensation .................................................... 225
Figure 125. GMCH System Memory Reference Voltage Generation Circuit........................ 225
Figure 126. GMCH HDVREF[2:0] Reference Voltage Generation Circuit ............................ 227
Figure 127. GMCH HAVREF Reference Voltage Generation Circuit ................................... 227
Figure 128. GMCH HCCVREF Reference Voltage Generation Circuit................................. 227
Figure 129. Primary Side of the Motherboard Layout .......................................................... 228
Figure 130. Secondary Side of the Motherboard Layout ...................................................... 228
Figure 131. GMCH HXRCOMP and HYRCOMP Resistive Compensation .......................... 229
Figure 132. GMCH HXSWING and HYSWING Reference Voltage Generation Circuit ....... 229
Figure 133. Example Analog Supply Filter ............................................................................ 230
Figure 134. Routing Illustration for INIT# .............................................................................. 241
Figure 135. Voltage Translation Circuit for PROCHOT#....................................................... 241
Figure 136. VCCIOPLL, VCCA and VSSA Power Distribution ............................................. 241
Figure 137. Mobile Intel Pentium 4 Processor-M Power Up Sequence................................ 244
Figure 138. Routing Illustration for INIT# (for Intel Celeron M Processor)............................ 246
Figure 139. Voltage Translation Circuit for PROCHOT# (for Intel Celeron M Processor).... 246
Figure 140. Clock Power-down Implementation ................................................................... 248
Figure 141. Reference Voltage Level for SMVREF .............................................................. 250
Figure 142. Intel 852GM GMCH HXSWING and HYSWING Reference Voltage Generation
Circuit ..................................................................................................................... 251
Figure 143. DPMS Clock Implementation ............................................................................. 253
Figure 144. Intel 852GM GMCH Power-up Sequence.......................................................... 256
Figure 145. Single or Locally Generated GMCH & ICH4-M HIVREF/HI_VSWING Circuit... 262
Figure 146. Single Generated GMCH & ICH4-M VSWING/VREF Reference Voltage/ Local
Voltage Divider Circuit for VSWING/VREF............................................................ 263
Figure 147. External Circuitry for the RTC ............................................................................ 264
Figure 148. Good Downstream Power Connection............................................................... 267
Figure 149. LAN_RST# Design Recommendation ............................................................... 269