Specification Update
Summary Tables of Changes
12 Specification Update
NO A1 Plan ERRATA
AM65 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
AM66 X Plan Fix REP Store Instructions in a Specific Situation may cause the Processor to Hang
AM67 X Plan Fix
Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction
Followed by SYSRET
AM68 X No Fix VM Bit is Cleared on Second Fault Handled by Task Switch from Virtual-8086 (VM86)
AM69 X No Fix The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
AM70 X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate
AM71 X Plan Fix
CPUID Reports Architectural Performance Monitoring Version 2 is Supported, When
Only Version 1 Capabilities are Available
AM72 X No Fix Unaligned Accesses to Paging Structures May Cause the Processor to Hang
AM73 X Plan Fix
Update of Attribute Bits on Page Directories without Immediate TLB Shootdown May
Cause Unexpected Processor Behavior
AM74 X Plan Fix Invalid Instructions May Lead to Unexpected Behavior
AM75 X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown
AM76 X Plan Fix
Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some
Decoded Instructions
AM77 X No Fix
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly
for PMULUDQ Instruction
AM78 X No Fix
Writing Shared Unaligned Data that Crosses a Cache Line without Proper
Semaphores or Barriers May Expose a Memory Ordering Issue
AM79 X Plan Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without
TLB Shootdown May Cause Unexpected Processor Behavior
AM80 X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AM81 X No Fix
INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain
Conditions
AM82 X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault
AM83 X Plan Fix
The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and
SYSRET
AM84 X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI
AM85 X No Fix ODLAT Does Not Match on Written Data When the FSB Ratio is 6:1
AM86 X No Fix Store Ordering May be Incorrect between WC and WP Memory
AM87 X Plan Fix
Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 (30AH) and
MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When the Processor is Reset
AM88 X No Fix
Updating Code Page Directory Attributes without TLB Invalidation May Result in
Improper Handling of Code #PF
AM89
X Plan Fix Performance Monitoring Event BR_INST_RETIRED May Count CPUID Instructions as
Branches
AM90 X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count