Uncore Manual

Reference Number: 329468-002 121
Uncore Performance Monitoring
Power Control (PCU) Performance Monitoring
DELAYED_C_STATE_ABORT_CORE0
• Title: Deep C State Rejection - Core 0
• Category: Delayed C-State Events
• Event Code: 0x17
• Extra Select Bit: Y
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Number of times that a deep C state was requested, but the delayed C state algo-
rithm “rejected” the deep sleep state. In other words, a wake event occurred before the timer
expired that causes a transition into the deeper C state.
DELAYED_C_STATE_ABORT_CORE1
• Title: Deep C State Rejection - Core 1
• Category: Delayed C-State Events
• Event Code: 0x18
• Extra Select Bit: Y
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Number of times that a deep C state was requested, but the delayed C state algo-
rithm “rejected” the deep sleep state. In other words, a wake event occurred before the timer
expired that causes a transition into the deeper C state.
DELAYED_C_STATE_ABORT_CORE10
• Title: Deep C State Rejection - Core 10
• Category: Delayed C-State Events
• Event Code: 0x21
• Extra Select Bit: Y
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Number of times that a deep C state was requested, but the delayed C state algo-
rithm “rejected” the deep sleep state. In other words, a wake event occurred before the timer
expired that causes a transition into the deeper C state.
DELAYED_C_STATE_ABORT_CORE11
• Title: Deep C State Rejection - Core 11
• Category: Delayed C-State Events
• Event Code: 0x22
• Extra Select Bit: Y
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Number of times that a deep C state was requested, but the delayed C state algo-
rithm “rejected” the deep sleep state. In other words, a wake event occurred before the timer
expired that causes a transition into the deeper C state.
DELAYED_C_STATE_ABORT_CORE12
• Title: Deep C State Rejection - Core 12
• Category: Delayed C-State Events
• Event Code: 0x23
• Extra Select Bit: Y
• Max. Inc/Cyc:. 1, Register Restrictions: 0-3
• Definition: Number of times that a deep C state was requested, but the delayed C state algo-
rithm “rejected” the deep sleep state. In other words, a wake event occurred before the timer
expired that causes a transition into the deeper C state.