Intel Celeron Processor in the 478-Pin Package at 1.80 GHz Datasheet

Datasheet 47
Intel
®
Celeron
®
Processor in the 478-Pin Package
NOTES:
1. These specifications are measured at the processor silicon.
2. BCLK period is 10 ns.
3. AF is referenced to BCLK[1:0].
NOTES:
1. These specifications are specified at the processor silicon.
2. This table assumes a 33 MHz time domain.
Table 24. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Duration (ns)
AF = 1
Pulse
Duration (ns)
AF = 0.1
Pulse
Duration (ns)
AF = 0.01
2.30 –0.585 0.24 2.4 20.0
2.25 –0.535 0.44 4.4 20.0
2.20 –0.485 0.88 8.8 20.0
2.15 –0.435 1.64 16.4 20.0
2.10 –0.385 3.0 20.0 20.0
2.05 –0.335 5.4 20.0 20.0
2.00 –0.285 10.0 20.0 20.0
1.95 –0.235 18.8 20.0 20.0
1.90 –0.185 20.0 20.0 20.0
1.85 –0.135 20.0 20.0 20.0
1.80 –0.085 20.0 20.0 20.0
Table 25. Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/Undershoot
Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Duration (ns)
AF = 1
Pulse
Duration (ns)
AF = 0.1
Pulse
Duration (ns)
AF = 0.01
2.30 –0.585 0.72 7.2 60.0
2.25 –0.535 1.32 13.2 60.0
2.20 –0.485 2.64 26.4 60.0
2.15 –0.435 4.92 49.2 60.0
2.10 –0.385 9.0 60.0 60.0
2.05 –0.335 16.2 60.0 60.0
2.00 –0.285 30.0 60.0 60.0
1.95 –0.235 56.4 60.0 60.0
1.90 –0.185 60.0 60.0 60.0
1.85 –0.135 60.0 60.0 60.0
1.80 –0.085 60.0 60.0 60.0