Specification Update
Summary Tables of Changes
10 Specification Update
NO A1 Plan ERRATA
AM14 X No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not be Accurate
AM15 X No Fix
Performance Monitoring Event For Number Of Reference Cycles When The Processor
Is Not Halted (3CH) Does Not Count According To The Specification
AM16 X No Fix
Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address
Translations
AM17 X No Fix Code Segment limit violation may occur on 4 Gigabyte limit check
AM18 X Plan Fix FP Inexact-Result Exception Flag May Not Be Set
AM19 X Plan Fix
Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed
by RSM instruction before Restoring the Architectural State from SMRAM
AM20 X Plan Fix Sequential Code Fetch to Non-canonical Address May have Nondeterministic Results
AM21 X No Fix The PECI Controller Resets to the Idle State
AM22 X No Fix
Some Bus Performance Monitoring Events May Not Count Local Events under Certain
Conditions
AM23 X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
AM24 X No Fix
General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation
above 4-G Limit
AM25 X No Fix EIP May be Incorrect after Shutdown in IA-32e Mode
AM26 X No Fix
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When Execute
Disable Bit is Not Supported
AM27 X Plan Fix
(E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast
String REP STOS With Large Data Structures
AM28 X Plan Fix
Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired
(C0H) May Not Be Accurate
AM29 X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect
AM30 X Plan Fix
Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction
Execution Results
AM31 X No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock
Count (IA32_MPERF) May Contain Incorrect Data after a Machine Check Exception
(MCE)
AM32 X No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to
Partial Memory Update
AM33 X No Fix Split Locked Stores May not Trigger the Monitoring Hardware
AM34 X Plan Fix
REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >=
0X100000000
AM35 X Plan Fix
FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a
Wrap to a Misaligned Base Address (Alignment <= 0x10h) May Cause FPU
Instruction or Operand Pointer Corruption
AM36 X Plan Fix
PREFETCHh Instruction Execution under Some Conditions May Lead to Processor
Livelock
AM37 X Plan Fix
PREFETCHh Instructions May Not be Executed when Alignment Check (AC) is
Enabled