Specification Update

Errata
Specification Update
41
AT69. Performance Monitoring Events for L1 and L2 Miss May Not be
Accurate
Problem: Performance monitoring events 0CBh with an event mask value of 02h or 08h
(MEM_LOAD_RETIRED.L1_LINE_MISS or
MEM_LOAD_RETIRED.L2_LINE_MISS) may under count the cache miss
events.
Implication: Performance monitoring events 0CBh with an event mask value of 02h or 08h
may show a count which is lower than expected; the amount by which the
count is lower is dependent on other conditions occurring on the same load
that missed the cache.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AT70. CPUID Reports Architectural Performance Monitoring Version 2 is
Supported, When Only Version 1 Capabilities are Available
Problem: CPUID leaf 0Ah reports the architectural performance monitoring version that
is available in EAX[7:0]. Due to this erratum CPUID reports the supported
version as 2 instead of 1.
Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in
comparison to which features are actually supported.
Workaround: Software should use the recommended enumeration mechanism described in
the Architectural Performance Monitoring section of the Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 3: System Programming
Guide.
Status: For the steppings affected, see the Summary Tables of Changes.
AT71. Unaligned Accesses to Paging Structures May Cause the Processor to
Hang
Problem: When an unaligned access is performed on paging structure entries,
accessing a portion of two different entries simultaneously, the processor
may live lock.
Implication: When this erratum occurs, the processor may live lock causing a system
hang.
Workaround: Do not perform unaligned accesses on paging structure entries.
Status: For the steppings affected, see the Summary Tables of Changes.