Intel Celeron Processor in the 478-Pin Package at 1.80 GHz Datasheet

78 Datasheet
Intel
®
Celeron
®
Processor in the 478-Pin Package
TESTHI[12:8]
TESTHI[5:0]
Input
TESTHI[12:8] and TESTHI[5:0] must be connected to a V
CC power source
through a resistor for proper processor operation. See Section 2.4 for more
details.
THERMDA Other Thermal Diode Anode. See Section 7.3.1.
THERMDC Other Thermal Diode Cathode. See Section 7.3.1.
THERMTRIP# Output
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor which is configured to trip at approximately 135°C. Upon
assertion of THERMTRIP#, the processor will shut off its internal clocks (thus
halting program execution) in an attempt to reduce the processor junction
temperature. To protect the processor, its core voltage (V
CC) must be removed
following the assertion of THERMTRIP#. See Figure 13 and Table 16 for the
appropriate power down sequence and timing requirements. Once activated,
THERMTRIP# remains latched until RESET# is asserted. While the assertion of
the RESET# signal will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will again be
asserted after RESET# is de-asserted.
TMS Input
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRDY# Input
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all system bus agents.
TRST# Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset. This can be done with a 680
Ω pull-down
resistor.
V
CCA Input
V
CCA provides isolated power for the internal processor core PLLs. Refer to the
appropriate Platform Design Guide for complete implementation details.
V
CCIOPLL Input
V
CCIOPLL provides isolated power for internal processor system bus PLLs. Follow
the guidelines for V
CCA, and refer to the appropriate Platform Design Guide for
complete implementation details.
VCC
SENSE
Output
VCC
SENSE
is an isolated low impedance connection to processor core power
(V
CC). It can be used to sense or measure power near the silicon with little noise.
VCCVID Input
1.2 V are required to be supplied to the VCCVID pin if the platform is going to
support the Pentium
®
processor with 512 KB L2 cache on .13 micron process.
This requirement is to enable the platform to be upgradeable to the
Pentium
®
processor with 512 KB L2 cache on 0.13 micron process and is not
necessary if the platform will only support the Celeron processor in the 478-pin
package. Refer to the Pentium
®
4 Processor with 512 KB L2 Cache on 0.13
Micron Process Datasheet and the appropriate Platform Design Guide for more
information.
VID[4:0] Output
VID[4:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages (V
CC). These pins are not signals, but are either an open circuit
or a short circuit to V
SS on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are needed to cleanly
support processor voltage specification variations. See Table 2 for definitions of
these pins. The power supply must supply the voltage that is requested by these
pins, or disable itself.
V
SSA Input VSSA is the isolated ground for internal PLLs.
V
SSSENSE
Output
V
SSSENSE
is an isolated low impedance connection to processor core VSS. It can
be used to sense or measure ground near the silicon with little noise
Table 32. Signal Description (Sheet 7 of 7)
Name Type Description