Intel Celeron Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Process Datasheet

Intel
®
Celeron
®
Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
6 Datasheet
List of Tables
1 Processor Identification.......................................................................................11
2 System Bus Clock in Deep Sleep Mode (Differential Mode only) .......................16
3 Voltage Identification Definition ..........................................................................20
4 System Bus Signal Groups ................................................................................23
5 Frequency Select Truth Table for BSEL[1:0] ......................................................24
6 Absolute Maximum Ratings ................................................................................25
7 Voltage and Current Specifications.....................................................................26
8 Power Supply Current Slew Rate (dIcccore/dt)...................................................27
9 Vcc Static & Transient Tolerance........................................................................28
10 AGTL Signal Group Levels Specifications ..........................................................29
11 Non-AGTL Signal Group Levels Specifications ..................................................29
12 3.3 Volt CMOS Output Signal Group DC Specifications .....................................30
13 Processor AGTL Bus Specifications ...................................................................30
14 System Bus Timing Specifications (Single-Ended Clock) ...................................31
15 System Bus Timing Specifications (Differential Clock) .......................................32
16 Valid System Bus to Core Frequency Ratios .....................................................33
17 System Bus Timing Specifications (AGTL Signal Group) ...................................33
18 System Bus Timing Specifications (CMOS Signal Group)..................................33
19 System Bus Timing Specifications (Reset Conditions) ......................................34
20 System Bus Timing Specifications (APIC Clock and APIC I/O) ..........................34
21 System Bus Timing Specifications (TAP Connection) ........................................35
22 Platform Power-On Timings................................................................................36
23 BCLK (Single-Ended Clock Mode) Signal Quality Specifications for
Simulation at the Processor Pins ........................................................................41
24 BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality
Specifications for Simulation at the Processor Pins............................................41
25 AGTL Signal Groups Ringback Tolerance Specifications at the
Processor Pins....................................................................................................42
26 Example Platform Information.............................................................................45
27 100 MHz AGTL Signal Group Overshoot/Undershoot Tolerance ......................46
28 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance........................48
29 Signal Ringback Specifications for Non-AGTL Signal Simulation at the
Processor Pins....................................................................................................49
30 Processor Thermal Design Power ..................................................................... 51
31 THERMTRIP# Time Requirement.......................................................................51
32 Thermal Diode Parameters.................................................................................52
33 Thermal Diode Interface......................................................................................52
34 The Processor Package Dimensions ..................................................................54
35 Processor Case Loading Parameters .................................................................54
36 Signal Listing in Order by Signal Name ..............................................................58
37 Signal Listing in Order by Pin Number ................................................................63
38 Boxed Processor Fan Heatsink Spatial Dimensions...........................................70
39 Fan Heatsink Power and Signal Specifications...................................................72
40 Signal Description ...............................................................................................73
41 Output Signals.....................................................................................................80
42 Input Signals .......................................................................................................80
43 Input/Output Signals (Single Driver)....................................................................81
44 Input/Output Signals (Multiple Driver) .................................................................82