Uncore Manual

Reference Number: 329468-002 21
Uncore Performance Monitoring
UBox Performance Monitoring
• The master for reading and writing physically distributed registers across physical processor
using the Message Channel.
• The UBox is the intermediary for interrupt traffic, receiving interrupts from the system and
dispatching interrupts to the appropriate core.
• The UBox serves as the system lock master used when quiescing the platform (e.g., Intel
®
QPI
bus lock).
2.2.2 UBox Performance Monitoring Overview
The UBox supports event monitoring through two programmable 44-bit wide counters
(U_MSR_PMON_CTR{1:0}), and a 48-bit fixed counter which increments each u-clock. Each of these
counters can be programmed (U_MSR_PMON_CTL{1:0}) to monitor any UBox event.
For information on how to setup a monitoring session, refer to Section 2.1, “Uncore Per-Socket
Performance Monitoring Control”.
2.2.2.1 UBox PMON Registers - On Overflow and the Consequences (PMI/Freeze)
If an overflow is detected from a UBox performance counter and its overflow enable bit
(U_MSR_PMON_CTLx.ov_en) has been set to 1, the overflow bit is set at the box level
(U_MSR_PMON_BOX_STATUS.ov) and the freeze signal is broadcast to other boxes.
When the global logic in the UBox receives the overflow signal, the
U_MSR_PMON_GLOBAL_STATUS.ov_u bit is set (see Table 2-3, “U_MSR_PMON_GLOBAL_STATUS
Register – Field Definitions”) and a PMI can be generated.
Once a freeze has occurred, in order to see a new freeze, the overflow responsible for the freeze must
be cleared by setting the corresponding bit in U_MSR_PMON_BOX_STATUS.ov and
U_MSR_PMON_GLOBAL_STATUs.ov_u to 1. Assuming all the counters have been locally enabled (.en
bit in control registers meant to monitor events) and the overflow bit(s) has been cleared, the UBox
is prepared for a new sample interval. Once the global controls have been re-enabled (Section 2.1.4,
“Enabling a New Sample Interval from Frozen Counters”), counting will resume.
2.2.3 UBox Performance Monitors
MSR Name
MSR
Address
Size
(bits)
Description
U_MSR_PMON_CTR1 0x0C17 64 U-Box PMON Counter 1
U_MSR_PMON_CTR0 0x0C16 64 U-Box PMON Counter 0
U_MSR_PMON_BOX_STATUS 0x0C15 32 U-Box PMON Box-Wide Status
U_MSR_PMON_CTL1 0x0C11 64 U-Box PMON Control for Counter 1
U_MSR_PMON_CTL0 0x0C10 32 U-Box PMON Control for Counter 0
U_MSR_PMON_UCLK_FIXED_CTR 0x0C09 64 U-Box PMON UCLK Fixed Counter
U_MSR_PMON_UCLK_FIXED_CTL 0x0C08 32 U-Box PMON UCLK Fixed Counter Control