Intel Celeron Processor in the 478-Pin Package at 1.80 GHz Datasheet

86 Datasheet
Intel
®
Celeron
®
Processor in the 478-Pin Package
7.2.5 Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state
upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is
in the Stop Grant state. SLP# assertions while the processor is not in the Stop Grant state is out of
specification and may result in unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK[1:0] inputs. (See Section 7.2.6). Once in the Sleep or Deep Sleep
states, the SLP# pin must be de-asserted if another asynchronous system bus event needs to occur.
The SLP# pin has a minimum assertion of one BCLK period.
When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.
7.2.6 Deep Sleep State—State 6
Deep Sleep state is the lowest power state the processor can enter while maintaining context. Deep
Sleep state is entered by stopping the BCLK[1:0] inputs (after the Sleep state was entered from the
assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK[1:0] is
stopped. To provide maximum power conservation hold the BLCK0 input at V
OL
and the BCLK1
input at V
OH
during the Deep Sleep state. Stopping the BCLK input lowers the overall current
consumption to leakage levels.
To re-enter the Sleep state, the BLCK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior. The processor has to stay in
Deep Sleep mode for minimum of 25 µs.
When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions.