Specification Update

Summary Tables of Changes
Specification Update
11
NO A1 Plan ERRATA
AT35
X Plan Fix
PREFETCHh Instruction Execution under Some Conditions May Lead to Processor
Livelock
AT36
X Plan Fix
PREFETCHh Instructions May Not be Executed when Alignment Check (AC) is
Enabled
AT37
X Plan Fix
Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory Image May
Be Unexpectedly All 1's after FXSAVE
AT38
X Plan Fix Performance Monitor IDLE_DURING_DIV (18h) Count May Not be Accurate
AT39
X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AT40
X Plan Fix
SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the
New EFLAGS.TF
AT41
X No Fix
Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority
Interrupts/Exceptions
AT42
X Plan Fix IA32_FMASK is Reset during an INIT
AT43
X No Fix
Code Breakpoint May Be Taken after POP SS Instruction if it is followed by an
Instruction that Faults
AT44
X No Fix Last Branch Records (LBR) Updates May be Incorrect after a Task Switch
AT45
X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
AT46
X No Fix INIT Does Not Clear Global Entries in the TLB
AT47
X Plan Fix
Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable
Behavior
AT48
X Plan Fix BTS Message May Be Lost When the STPCLK# Signal is Active
AT49
X No Fix
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 2
48
May
Terminate Early
AT50
X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries
with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-
Ordering Violations.
AT51
X No Fix MOV To/From Debug Registers Causes Debug Exception
AT52
X No Fix
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in
64-bit Mode
AT53
X No Fix A Thermal Interrupt is Not Generated when the Current Temperature is Invalid
AT54
X No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable
System Behavior
AT55
X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception
AT56
X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
AT57
X Plan Fix CPL-Qualified BTS May Report Incorrect Branch-From Instruction Address
AT58
X Plan Fix PEBS Does Not Always Differentiate Between CPL-Qualified Events