Intel Celeron Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 43
System Bus Signal Quality Specifications
Table 25. Ringback Specifications for PWRGOOD Input and TAP Signal Group
Signal Group Transition
Maximum Ringback
(with Input Diodes Present)
Unit Figure Notes
1,2,3,4
NOTES:
1. All signal integrity specifications are measured at the processor silicon.
2. Unless otherwise noted, all specifications in this table apply to all Celeron processor on 0.13 micron process
frequencies.
3. See Section 3.3 for maximum allowable overshoot.
4. See Section 2.11 for the DC specifications.
TAP and PWRGOOD 0 → 1 Vt+(max) TO Vt-(max) V 24
TAP and PWRGOOD 1 → 0 Vt-(min) TO Vt+(min) V 25
Figure 22. Low-to-High System Bus Receiver Ringback Tolerance
GTLREF
V
CC
Noise
Margin
+10% GTLREF
-10% GTLREF
V
SS
Figure 23. High-to-Low System Bus Receiver Ringback Tolerance
Noise
Margin
GTLREF
+10% GTLREF
-10% GTLREF
V
CC
V
SS