Specification Update

Summary Tables of Changes
Specification Update 13
NO A1 Plan ERRATA
AM91
X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of
the Monitoring Hardware
AM92 X Plan Fix False Level One Data Cache Parity Machine-Check Exceptions May be Signaled
AM93
X No Fix CPUID Incorrectly Reports Support for C2/C2E on Some Processors
AM94
X No Fix PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR Information
AM95
X No Fix A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to
an MTRR Mask
AM96
X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
Transitions
AM97
X No Fix A WB Store Following a REP STOS/MOVS May Lead to Memory-Ordering Violations
AM98
X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache
AM99
X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang
or a Machine Check Exception
AM100
X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering
Violations
AM101
X No Fix RSM Instruction Execution under Certain Conditions May Cause Processor Hang or
Unexpected Instruction Execution Results
AM102
X No Fix NMIs May Not Be Blocked by a VM-Entry Failure
AM103
X No Fix
CPUID Extended Feature Does Not Report Intel® Thermal Monitor
2 Support Correctly
AM104
X No Fix
Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown
AM105
X No Fix
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error Reporting
Enable Correctly
Number SPECIFICATION CHANGES
- There are no Specification Changes in this Specification Update revision.
Number SPECIFICATION CLARIFICATIONS
AM1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Number DOCUMENTATION CHANGES
- There are no Documentation Changes in this Specification Update revision.