Intel Celeron Processor in the 478-Pin Package at 1.80 GHz Datasheet

Datasheet 41
Intel
®
Celeron
®
Processor in the 478-Pin Package
NOTES:
1. All signal integrity specifications are measured at the processor silicon.
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
3. See Section 2.10 for the DC specifications.
Table 21. Ringback Specifications for TAP and PWRGOOD Signal Groups
Signal Group Transition
Maximum Ringback
(with Input Diodes Present)
Unit Figure Notes
TAP and PWRGOOD 0
→ 1Vt+ (max) to Vt– (max) V 19 1,2,3
TAP and PWRGOOD 1
→ 0Vt– (min) to Vt+ (min) V 20 1,2,3
Figure 17. Low-to-High System Bus Receiver Ringback Tolerance
GTLREF
V
CC
Noise Margin
+100 mV
-100 mV
V
SS
Figure 18. High-to-Low System Bus Receiver Ringback Tolerance
V
CC
Noise Margin
V
SS
GTLREF
+100 mV
-100 mV