Specification Update

Errata
Specification Update 53
AM97. A WB Store Following a REP STOS/MOVS May Lead to Memory-Ordering
Violations
Problem: Under certain conditions, as described in the Software Developers Manual section
“Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors”, the processor performs REP MOVS or REP STOS as fast strings. Due to
this erratum, stores of WB memory type to a cache line previously written by a
preceding fast string instruction may be observed before a string store.
Implication: A store may be observed before a previous string store. Intel has not observed this
erratum with any commercially available software.
Workaround: Software desiring strict ordering of string operations should add an MFENCE or
SFENCE instruction after a fast string operation.
Status: For the steppings affected, see the Summary Tables of Changes.
Status: Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache
Problem: A livelock may be observed in rare conditions when instruction fetch causes
multiple level one data cache snoops.
Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with
any commercially available software.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.