Guide

Intel Celeron M Processor Front Side Bus Design Guidelines
R
Intel
®
852GM Chipset Platform Design Guide 69
Figure 28. Routing Illustration for Topology 2C
CPU
ICH4-M
L1
Table 26. Layout Recommendations for Topology 2C
L1 Transmission Line Type
0.5” – 12.0” Micro-strip
0.5” – 12.0” Strip-line
5.5.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH
– INIT#
The signal INIT# should adhere to the following routing and layout recommendations. Table 27 lists the
recommended routing requirements for the INIT# signal of the ICH4-M. The routing guidelines allow
both signals to be routed as either micro-strip or strip-lines using 55 Ω ± 15% characteristic trace
impedance. Figure 29 shows the recommended implementation for providing voltage translation
between the ICH4-M’s INIT# voltage signaling level and any firmware hub (FWH) that utilizes a 3.3-V
interface voltage (shown as a supply V_IO_FWH). See Section 5.5.8 for more details on the voltage
translator circuit.
Series resistor Rs is a component of the voltage translator logic circuit and serves as a driver isolation
resistor. Rs is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1, to
emphasize the placement of Rs with respect to Q1. The placement of Rs a distance of L3 before the Q1
BJT is a specific implementation of the generalized voltage translator circuit shown in Figure 30. The
routing recommendations of transmission line L3 in Figure 29 is listed in Table 27 and Rs should be
placed at the beginning of the T-split of the trace from the ICH4-M’s INIT# pin.