Guide

Intel Celeron M Processor Front Side Bus Design Guidelines
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Intel
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852GM Chipset Platform Design Guide 57
Figure 21. Layer 6 FSB Source Synchronous Signals GND Referencing to Layer 5
In a similar way, Figure 22 illustrates a recommended layout and stack-up example of how another
group of FSB source synchronous DATA and ADDRESS signals can reference ground planes on both
Layer 2 and Layer 4. Note that in the socket cavity of the processor, Layer 3 is used for VCC core power
delivery to reduce the I*R drop. However, outside of the socket cavity Layer 3 signals are routed below
a solid Layer 2 ground plane and also Layer 4 is converted to a ground flood under the shadow of the
FSB signals routing between the processor and the GMCH.