Guide

I/O Subsystem
R
170 Intel
®
852GM Chipset Platform Design Guide
10.5.1. IOAPIC Disabling Options
10.5.1.1. Recommended Implementation
Intel recommends that IOAPIC be disabled in software while the connections to the board are as shown
in Figure 85. Software can be used to turn off PICCLK from clock generator.
To disable IOAPIC in BIOS:
• ICH4-M: D31:F0; Offset: D1; bit 7:8
• Mobile Pentium 4 Processor-M Processor: MSR 1Bh bit 11
Figure 85. Minimum IOAPIC Disable Topology
CK-408
ICH4-M
PCIF0 APICD0
APICD1
33 Ω
10 kΩ
APICLK
10.6. SMBus 2.0/SMLink Interface
The SMBus interface on the ICH4-M uses two signals SMBCLK and SMBDATA to send and receive
data from components residing on the bus. These signals are used exclusively by the SMBus Host
Controller. The SMBus Host Controller resides inside the ICH4-M.
The ICH4-M incorporates an SMLink interface supporting Alert-on-LAN*, Alert-on-LAN2*, and a
slave functionality. It uses two signals SMLINK[1:0]. SMLINK[0] corresponds to an SMBus clock
signal and SMLINK[1] corresponds to an SMBus data signal. These signals are part of the SMB Slave
Interface.
For Alert-on-LAN* functionality, the ICH4-M transmits heartbeat and event messages over the
interface. When using the Intel
®
82562EM Platform LAN Connect Component, the ICH4-M’s
integrated LAN Controller will claim the SMLink heartbeat and event messages and send them out over
the network. An external, Alert-on-LAN2*-enabled LAN Controller (i.e. Intel 82562EM 10/100 Mbps
Platform LAN Connect) will connect to the SMLink signals to receive heartbeat and event messages, as
well as access the ICH4-M SMBus Slave Interface. The slave interface function allows an external
micro-controller to perform various functions. For example, the slave write interface can reset or wake a
system, generate SMI# or interrupts, and send a message. The slave read interface can read the system
power state, read the watchdog timer status, and read system status bits.
Both the SMBus Host Controller and the SMBus Slave Interface obey the SMBus 1.0 protocol, so the
two interfaces can be externally wire-OR’ed together to allow an external management ASIC (such as
Intel 82562EM 10/100 Mbps Platform LAN Connect) to access targets on the SMBus as well as the
ICH4-M Slave Interface. Additionally, the ICH4-M supports slave functionality, including the Host
Notify protocol, on the SMLink pins. Therefore, in order to be fully compliant with the SMBus 2.0
specification (which requires the Host Notify cycle), the SMLink and SMBus signals
must be tied
together externally. This is done by connecting SMLink[0] to SMBCLK and SMLink[1] to SMBDATA.