Document

4 Datasheet
Figures
1 Package-Level Low-Power States................................................................................11
2 Core Low-Power States .............................................................................................12
3 Active VCC and ICC Loadline Standard Voltage.............................................................26
4 1-MB Fused Micro-FCPGA Processor Package Drawing (1 of 2)........................................30
5 1-MB Fused Micro-FCPGA Processor Package Drawing (2 of 2)........................................31
6 1-MB Micro-FCPGA Processor Package Drawing (1 of 2).................................................32
7 1-MB Micro-FCPGA Processor Package Drawing (2 of 2).................................................33
Tables
1 Coordination of Core-Level Low-Power States at the Package Level .................................11
2 Voltage Identification Definition..................................................................................18
3 BSEL[2:0] Encoding for BCLK Frequency......................................................................22
4 FSB Pin Groups ........................................................................................................22
5 Processor Absolute Maximum Ratings..........................................................................24
6 DC Voltage and Current Specifications.........................................................................24
7 FSB Differential BCLK Specifications............................................................................26
8 AGTL+ Signal Group DC Specifications ........................................................................27
9 CMOS Signal Group DC Specifications..........................................................................28
10 Open Drain Signal Group DC Specifications ..................................................................28
11 The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 1 of 2)..........................................................................................................34
12 The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 2 of 2)..........................................................................................................35
13 Pin Listing by Pin Name.............................................................................................37
14 Pin Listing by Pin Number..........................................................................................44
15 Signal Description.....................................................................................................53
16 Standard Voltage Power Specifications ........................................................................61
17 Thermal Diode ntrim and Diode Correction Toffset ........................................................63
18 Thermal Diode Interface............................................................................................63
19 Thermal Diode Parameters using Diode Mode ...............................................................63
20 Thermal Diode Parameters using Transistor Model ........................................................64