Intel Celeron Processor in the 478-Pin Package at 1.80 GHz Datasheet

42 Datasheet
Intel
®
Celeron
®
Processor in the 478-Pin Package
Figure 19. Low-to-High System Bus Receiver Ringback Tolerance for TAP and PWRGOOD
Buffers
Figure 20. High-to-Low System Bus Receiver Ringback Tolerance for TAP and PWRGOOD
Buffers
0.5 * Vcc
Vt+ (min)
Vt+ (max)
Vt- (max)
Vcc
Allowable Ringback
Vss
Threshold Region to switch
receiver to a logic 1.
0.5 * Vcc
Vt+ (min)
Vt- (max)
Vcc
Vss
Vt- (min)
Threshold Region to switch
receiver to a logic 0.
Allowable Ringback