Specification Update

Errata

AT88. Performance Monitoring Event MISALIGN_MEM_REF May Over Count

Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count

the number of memory accesses that cross an 8-byte boundary and are

blocked until retirement. Due to this erratum, the performance monitoring

event MISALIGN_MEM_REF also counts other memory accesses.

Implication: The performance monitoring event MISALIGN_MEM_REF may over count. The

extent of over counting depends on the number of memory accesses retiring

while the counter is active.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

AT89. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May

Prevent Triggering of the Monitoring Hardware

Problem: The MONITOR instruction is used to arm the address monitoring hardware for

the subsequent MWAIT instruction. The hardware is triggered on subsequent

memory store operations to the monitored address range. Due to this

erratum, REP STOS/MOVS fast string operations to the monitored address

range may prevent the actual triggering store to be propagated to the

monitoring hardware.

Implication: A logical processor executing an MWAIT instruction may not immediately

continue program execution if a REP STOS/MOVS targets the monitored

address range.

Workaround: Software can avoid this erratum by not using REP STOS/MOVS store

operations within the monitored address range.

Status: For the steppings affected, see the Summary Tables of Changes.

AT90. False Level One Data Cache Parity Machine-Check Exceptions May be

Signaled

Problem: Executing an instruction stream containing invalid instructions/data may

generate a false Level One Data Cache parity machine-check exception.

Implication: The false Level One Data Cache parity machine-check exception is reported

as an uncorrected machine-check error. An uncorrected machine-check error

is treated as a fatal exception by the operating system and may cause a

shutdown and/or reboot.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.