Specification Update

Errata

46 Specification Update

AT81. Page Access Bit May be Set Prior to Signaling a Code Segment Limit

Fault

Problem: If code segment limit is set close to the end of a code page, then due to this

erratum the memory page Access bit (A bit) may be set for the subsequent

page prior to general protection fault on code segment limit.

Implication: When this erratum occurs, a non-accessed page which is present in memory

and follows a page that contains the code segment limit may be tagged as

accessed.

Workaround: Erratum can be avoided by placing a guard page (non-present or non-

executable page) as the last page of the segment or after the page that

includes the code segment limit.

Status: For the steppings affected, see the Summary Tables of Changes.

AT82. The Stack Size May be Incorrect as a Result of VIP/VIF Check on

SYSEXIT and SYSRET

Problem: The stack size may be incorrect under the following scenario:

• The stack size was changed due to a SYSEXIT or SYSRET

• PVI (Protected Mode Virtual Interrupts) mode was enabled (CR4.PVI ==

• Both the VIF (Virtual Interrupt Flag) and VIP (Virtual Interrupt Pending)

flags of the EFLAGS register are set

Implication: If this erratum occurs the stack size may be incorrect, consequently this may

result in unpredictable system behavior. Intel has not observed this erratum

with any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.